RSD: RISC-V Out-of-Order Superscalar Processor

A Linux-capable RISC-V multicore for and by the world

BaseJump STL: A Standard Template Library for SystemVerilog

Test suite designed to check compliance with the SystemVerilog standard.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Source code repo for UVM Tutorial for Candy Lovers

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Network on Chip Implementation written in SytemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

A Fast, Low-Overhead On-chip Network

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

Generic Register Interface (contains various adapters)

Proposed RISC-V Composable Custom Extensions Specification

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Network on Chip for MPSoC

BlackParrot on Zynq

Simple template-based UVM code generator

Demo: how to create a custom EBRICK