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vivado.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Sun Nov 21 22:27:33 2021
# Process ID: 13876
# Current directory: F:/vivado_workspace/mycpu1
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent20128 F:\vivado_workspace\mycpu1\mycpu1.xpr
# Log file: F:/vivado_workspace/mycpu1/vivado.log
# Journal file: F:/vivado_workspace/mycpu1\vivado.jou
#-----------------------------------------------------------
start_gui
open_project F:/vivado_workspace/mycpu1/mycpu1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'E:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 984.875 ; gain = 0.000
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "F:/vivado_workspace/mycpu1/mycpu1.sim/sim_1/behav/xsim/simulate.log"
launch_simulation
Command: launch_simulation
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "F:/vivado_workspace/mycpu1/mycpu1.sim/sim_1/behav/xsim/simulate.log"
launch_simulation
Command: launch_simulation
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "F:/vivado_workspace/mycpu1/mycpu1.sim/sim_1/behav/xsim/simulate.log"
launch_simulation
Command: launch_simulation
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "F:/vivado_workspace/mycpu1/mycpu1.sim/sim_1/behav/xsim/simulate.log"
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a200tfbg676-2
Top: central
INFO: [Device 21-403] Loading part xc7a200tfbg676-2
WARNING: [Synth 8-2611] redeclaration of ansi port result is not allowed [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/alu.v:47]
WARNING: [Synth 8-2611] redeclaration of ansi port AluOp is not allowed [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/control.v:27]
WARNING: [Synth 8-6901] identifier 'PC' is used before its declaration [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:32]
WARNING: [Synth 8-6901] identifier 'alu_result' is used before its declaration [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:80]
WARNING: [Synth 8-6901] identifier 'RAM_ReadData' is used before its declaration [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:80]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1282.094 ; gain = 253.129
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'central' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:23]
INFO: [Synth 8-6157] synthesizing module 'my_inst_rom' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_inst_rom.v:1]
INFO: [Synth 8-6157] synthesizing module 'inst_rom' [F:/vivado_workspace/mycpu1/.Xil/Vivado-13876-ChantecPC/realtime/inst_rom_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'inst_rom' (1#1) [F:/vivado_workspace/mycpu1/.Xil/Vivado-13876-ChantecPC/realtime/inst_rom_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'my_inst_rom' (2#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_inst_rom.v:1]
WARNING: [Synth 8-689] width (8) of port connection 'addr' does not match port width (5) of module 'my_inst_rom' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:49]
INFO: [Synth 8-6157] synthesizing module 'control' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/control.v:1]
INFO: [Synth 8-251] store 鎸囦护 [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/control.v:49]
INFO: [Synth 8-6155] done synthesizing module 'control' (3#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/control.v:1]
INFO: [Synth 8-6157] synthesizing module 'regfile' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:23]
INFO: [Synth 8-251] debug reg we=1 i:x wData x [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:43]
WARNING: [Synth 8-567] referenced signal 'we' should be on the sensitivity list [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:40]
WARNING: [Synth 8-567] referenced signal 'wdata' should be on the sensitivity list [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:40]
WARNING: [Synth 8-567] referenced signal 'waddr' should be on the sensitivity list [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:40]
INFO: [Synth 8-6155] done synthesizing module 'regfile' (4#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/regfile.v:23]
INFO: [Synth 8-6157] synthesizing module 'alu' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/alu.v:24]
INFO: [Synth 8-6157] synthesizing module 'adder' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/adder.v:1]
INFO: [Synth 8-6155] done synthesizing module 'adder' (5#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/adder.v:1]
INFO: [Synth 8-251] debug alu code=4'bxxxx [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/alu.v:67]
INFO: [Synth 8-251] debug alu op1=32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx,op2=32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/alu.v:68]
INFO: [Synth 8-6155] done synthesizing module 'alu' (6#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/alu.v:24]
INFO: [Synth 8-6157] synthesizing module 'my_data_ram' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_data_ram.v:1]
INFO: [Synth 8-251] debug data_ram we=1 addr:x wdata:x [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_data_ram.v:13]
WARNING: [Synth 8-567] referenced signal 'addr' should be on the sensitivity list [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_data_ram.v:11]
WARNING: [Synth 8-567] referenced signal 'wdata' should be on the sensitivity list [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_data_ram.v:11]
INFO: [Synth 8-6157] synthesizing module 'data_ram' [F:/vivado_workspace/mycpu1/.Xil/Vivado-13876-ChantecPC/realtime/data_ram_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'data_ram' (7#1) [F:/vivado_workspace/mycpu1/.Xil/Vivado-13876-ChantecPC/realtime/data_ram_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'my_data_ram' (8#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/my_data_ram.v:1]
WARNING: [Synth 8-689] width (32) of port connection 'addr' does not match port width (5) of module 'my_data_ram' [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:128]
INFO: [Synth 8-6155] done synthesizing module 'central' (9#1) [F:/vivado_workspace/mycpu1/mycpu1.srcs/sources_1/new/central.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1336.941 ; gain = 307.977
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1336.941 ; gain = 307.977
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1336.941 ; gain = 307.977
---------------------------------------------------------------------------------
INFO: [Project 1-454] Reading design checkpoint 'f:/vivado_workspace/mycpu1/mycpu1.gen/sources_1/ip/inst_rom/inst_rom.dcp' for cell 'u_rom/myROM'
INFO: [Project 1-454] Reading design checkpoint 'f:/vivado_workspace/mycpu1/mycpu1.gen/sources_1/ip/data_ram/data_ram.dcp' for cell 'u_my_data_ram/myRAM'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1336.941 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1425.223 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
RTL Elaboration Complete: : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1551.348 ; gain = 522.383
31 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 1551.348 ; gain = 566.473
launch_simulation
Command: launch_simulation
boost::filesystem::remove: 另一个程序正在使用此文件，进程无法访问。: "F:/vivado_workspace/mycpu1/mycpu1.sim/sim_1/behav/xsim/simulate.log"
exit
INFO: [Common 17-206] Exiting Vivado at Sun Nov 21 22:31:19 2021...