EECS151/251A FPGA Labs SP21

For each lab, please find the instructions at /lab#/spec/spec.md

Lab 1: Due next lab (1/26, 1/27)

Lab 2:

Lab 3:

Lab 4:

Lab 5:

Lab 6:

Link to the Final Project for FPGA

• Link not available yet

Course Website

https://inst.eecs.berkeley.edu/~eecs151/sp22/

Resources

PYNQ-Z1 Reference Manual: https://reference.digilentinc.com/reference/programmable-logic/pynq-z1/reference-manual

Sample XDC file: https://reference.digilentinc.com/_media/reference/programmable-logic/pynq-z1/pynq-z1_c.zip

Xilinx 7-series CLB architecture: https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

Xilinx 7-series Memory Resources: https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

Xilinx 7-series DSP Slice: https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

Vivado 2019.1:https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html

Vivado Synthesis User Guide 2019.1: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Vivado Implementation User Guide 2019.1: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug904-vivado-implementation.pdf

Vivado IDE User Guide 2019.1: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug893-vivado-ide.pdf

Vivado Simulation (Tutorial) 2019.1: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug937-vivado-design-suite-simulation-tutorial.pdf