Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generat…

A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.