diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
index 552aea62df0..70c193320bc 100644
--- a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
+++ b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
@@ -375,8 +375,8 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
   val s2_parity_error       = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i)))
 
   for(i <- 0 until PortNumber){
-    io.errors(i).valid            := RegNext(s2_parity_error(i))
-    io.errors(i).report_to_beu    := RegNext(s2_parity_error(i))
+    io.errors(i).valid            := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire)))
+    io.errors(i).report_to_beu    := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire)))
     io.errors(i).paddr            := RegNext(RegNext(s2_req_paddr(i)))
     io.errors(i).source           := DontCare
     io.errors(i).source.tag       := RegNext(RegNext(s2_parity_meta_error(i)))
@@ -385,6 +385,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
     io.errors(i).opType           := DontCare
     io.errors(i).opType.fetch     := true.B
   }
+  XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!")
 
 
   /** exception and pmp logic **/
diff --git a/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala b/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
index d6b3153a8ec..9a76a447567 100644
--- a/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
+++ b/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
@@ -179,8 +179,8 @@ class ICacheReplacePipe(implicit p: Parameters) extends ICacheModule{
   val r2_parity_error      = RegNext(r2_parity_meta_error) || r2_parity_data_error
 
 
-  io.error.valid                := RegNext(r2_parity_error )
-  io.error.report_to_beu        := RegNext(r2_parity_error )
+  io.error.valid                := RegNext(r2_parity_error &&  RegNext(RegNext(r1_fire))) 
+  io.error.report_to_beu        := RegNext(r2_parity_error &&  RegNext(RegNext(r1_fire)))
   io.error.paddr                := RegNext(RegNext(r2_req.paddr))
   io.error.source.tag           := RegNext(RegNext(r2_parity_meta_error))
   io.error.source.data          := RegNext(r2_parity_data_error)
@@ -190,6 +190,7 @@ class ICacheReplacePipe(implicit p: Parameters) extends ICacheModule{
   io.error.opType.release       := RegNext(RegNext(r2_req.isRelease))
   io.error.opType.probe         := RegNext(RegNext(r2_req.isProbe))
 
+  XSError(r2_parity_error && RegNext(RegNext(r1_fire)), "ICache has parity error in ReplacePipe!")
 
 
   /*** for Release mux ***/