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Commits on Feb 3, 2022

• ftq: read entry fetch status one cycle ahead (OpenXiangShan#1450)

  Lingrui98

  authored
  f678dd9

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Commits on Feb 1, 2022

• l2tlb: req from missqueue doesn't cause prefetch (OpenXiangShan#1448)

  Lemover

  authored
  9413360

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• ICache <bug-fix>: fix meta error when reset (OpenXiangShan#1447)

  jinyue110

  authored
  e8e4462

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• Bump huancun (OpenXiangShan#1446)

  ljwljwljwljw

  authored
  6427650

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Commits on Jan 28, 2022

• SoC: timing opt (OpenXiangShan#1431)

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  ljwljwljwljw

  and

  poemonsense

  authored
  752db3a

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• parameters: reduce ghr length and make it calculated using a formula (OpenXiangShan#1442)

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  Lingrui98

  authored
  c7fabd0

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• ICache <timing>: move parity decode to pipeline (OpenXiangShan#1443)

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  jinyue110

  authored
  79b191f

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• mem: fix deadlock caused by datainvalid (OpenXiangShan#1445)

  AugustusWillisWang

  authored
  7169fdc

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• Adjusted reset signals (OpenXiangShan#1441)

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  ljwljwljwljw

  authored
  25cb35b

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Commits on Jan 26, 2022

• ICache : fix 2 potential rule violations according to TL specification (OpenXiangShan#1444)

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  jinyue110

  authored
  00240ba

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Commits on Jan 24, 2022

• Merge pull request OpenXiangShan#1439 from OpenXiangShan/no-oversize

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  Lingrui98

  authored
  03590d7

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Commits on Jan 23, 2022

• ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

  Lingrui98

  committed
  f4ebc4b

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• IFU <info>: add debug info for predecode redirect

  jinyue110

  committed
  5b3c20f

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• csr: fix xret mode check (OpenXiangShan#1440)

  AugustusWillisWang

  authored
  cb8f178

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• Fetch: optimization timing for IFU/ICache/IPrefetch (OpenXiangShan#1432)

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  jinyue110

  authored
  61e1db3

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• pmp: fix bug of l locks cfg's modification (OpenXiangShan#1438)

  Lemover

  authored
  ff1b5db

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Commits on Jan 22, 2022

• bpu: handle fall through error at stage 3

  Lingrui98

  committed
  62e6338

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• bpu,ftq: remove oversize logic

  Lingrui98

  committed
  a60a290

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• IFU <opt>: delete oversize logic

  

  jinyue110

  authored and

  Lingrui98

  committed
  1d01197

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• ICacheMainPipe <bug-fix>: fix tlb resp condition

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  jinyue110

  authored and

  Lingrui98

  committed
  a11ea8d

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• ICache <bug-fix> fix parity error condition

  

  jinyue110

  authored and

  Lingrui98

  committed
  38912d0

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• ICache <bug-fix> delete PMP check assertion

  

  jinyue110

  authored and

  Lingrui98

  committed
  c6c185a

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• ICacheMainPipe <timing>: move hit state change to s2

  

  jinyue110

  authored and

  Lingrui98

  committed
  30aee68

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• Ftq <timing>: delete flush condition for prefetch.req

  

  jinyue110

  authored and

  Lingrui98

  committed
  259b970

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• Frontend <timing>: add additional PMP checker

  

  jinyue110

  authored and

  Lingrui98

  committed
  56788a3

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• ICacheMainPipe <timing>: latch fetch req when tlb miss

  

  jinyue110

  authored and

  Lingrui98

  committed
  71e336f

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• IFU <timing>: f2_data select signal optimization

  

  jinyue110

  authored and

  Lingrui98

  committed
  0bca1cc

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• Merge pull request OpenXiangShan#1435 from OpenXiangShan/tage-4t

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  Lingrui98

  authored
  d3ec97b

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• ci: moved to BOSC servers (OpenXiangShan#1437)

  poemonsense

  authored
  da3b568

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Commits on Jan 20, 2022

• tage: fix a huge bug on bim res

  Lingrui98

  committed
  de9a09b

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• tage: recover to 4 tables

  Lingrui98

  committed
  51e26c0

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Commits on Jan 19, 2022

• bpu: add more detailed s3 redirect perf counters

  Lingrui98

  committed
  ced16aa

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• tage: fix a bug on bim update way mask

  Lingrui98

  committed
  0ff7f6b

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• sc: fix a bug on update threshold

  Lingrui98

  committed
  ff1cd59

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Commits on Jan 18, 2022

• tage: try to fix u reset algorithm

  Lingrui98

  committed
  c71ba9c

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