forked from SpenceKonde/ATTinyCore
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy path.travis.yml
581 lines (538 loc) · 84.1 KB
/
.travis.yml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
# This file is used to configure the Travis CI tests of ATTinyCore
# It's necessary to do this just for codespell
language: python
python: 3.6
env:
global:
# The Arduino IDE will be installed at APPLICATION_FOLDER/arduino
- APPLICATION_FOLDER="${HOME}/arduino-ide"
- SKETCHBOOK_FOLDER="${HOME}/Arduino"
- FULL_IDE_VERSION_LIST='("1.6.7" "1.6.9" "1.6.13" "1.8.6" "1.8.11")'
- LTO_IDE_VERSION_LIST='("1.6.11" "1.6.13" "1.8.6" "1.8.11")'
- MAX_PATH_SAFE_IDE_VERSION_LIST='("1.8.6" "1.8.11")'
matrix:
# Compile every example sketch for every library included with ATTinyCore for every board, every option, every installed IDE version
# Each line in the matrix will be run as a separate job in the Travis CI build
# attinyx4
# LTO=disable, chip=84, clock=8internal, eesave=aenable, bod=1v8, pinmapping=anew
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=20external, eesave=disable, bod=1v8, pinmapping=old
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=20external,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=old" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=2v7
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, bod=4v3
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=6external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=enable,chip=84,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# chip=44, clock=4external
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=44,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=44, clock=4internal
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=44,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=24, clock=1internal
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=24,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx4:LTO=disable,chip=84,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx4opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, chip=84, clock=8internal, eesave=aenable, bod=1v8, pinmapping=anew
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=44, clock=20external, eesave=disable, bod=1v8, pinmapping=old
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=44,clock=20external,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=old" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=2v7
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, bod=4v3
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=enable,chip=84,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx4opti:LTO=disable,chip=84,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=anew" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx5
# LTO=disable, TimerClockSource=default, chip=85, clock=8internal, eesave=aenable, bod=1v8
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=8internal,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=pll, clock=16pll, eesave=disable, bod=1v8
# PLL Timer source not compatible with Servo library and I can't add individual jobs for each library due to Travis CI's 200 job limit, so I can only do a single compilation to check this board configuration
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=pll,chip=85,clock=16pll,eesave=disable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=lowpll, clock=20external, bod=2v7
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=lowpll,chip=85,clock=20external,eesave=disable,bod=2v7,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=4v3
# The libraries have already been tested with F_CPU of 16000000UL in the clock=16pll job so only a single compilation is necessary to test the clock=16external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=16external,eesave=aenable,bod=4v3,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=12external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=enable,TimerClockSource=default,chip=85,clock=12external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# chip=45, clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=45,clock=8external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=25, clock=6external
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=25,clock=6external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=4external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=4internal,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=1internal,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=737external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=92external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=11external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=14external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=184external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=128internal
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=128internal,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=165pll
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5:LTO=disable,TimerClockSource=default,chip=85,clock=165pll,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx5opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, TimerClockSource=default, chip=85, clock=8internal, eesave=aenable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=8internal,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=pll, chip=45, clock=16pll, eesave=disable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=pll,chip=45,clock=16pll,eesave=disable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=lowpll, clock=20external, bod=2v7
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=lowpll,chip=85,clock=20external,eesave=disable,bod=2v7,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=4v3
# The libraries have already been tested with F_CPU of 16000000UL in the clock=16pll job so only a single compilation is necessary to test the clock=16external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=16external,eesave=aenable,bod=4v3,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=12external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=enable,TimerClockSource=default,chip=85,clock=12external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=8external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=737external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=92external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=11external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=14external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny25/45/85 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx5opti:LTO=disable,TimerClockSource=default,chip=85,clock=184external,eesave=aenable,bod=1v8,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx8
# LTO=disable, chip=88, clock=16external (external clock), eesave=aenable, bod=1v8
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal, eesave=disable, bod=1v8
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=1internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal, eesave=disable, bod=1v8
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=1internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, bod=2v7
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=enable,chip=88,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# chip=48, bod=4v3
# BOD doesn't affect compilation so only a single compilation needs to be done to check the bod=4v3 option
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=48,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx8opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, chip=88, clock=8internal, eesave=aenable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=88,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=48, eesave=disable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=88,clock=8internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, bod=2v7, clock=16external (external clock)
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=enable,chip=88,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# bod=4v3
# BOD doesn't affect compilation so only a single compilation needs to be done to check the bod=4v3 option
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=48,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx7
# LTO=disable, chip=167, clock=8internal, eesave=aenable, bod=1v8, pinmapping=new
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=87, clock=20external, eesave=disable, bod=1v8, pinmapping=old
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=87,clock=20external,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=old" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=2v7
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, bod=4v3
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=6external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=enable,chip=167,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=4external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7:LTO=disable,chip=167,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx7opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, chip=167, clock=8internal, eesave=aenable, bod=1v8, pinmapping=new
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=8internal,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=87, clock=16external, eesave=disable, bod=1v8, pinmapping=old
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=87,clock=16external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=old" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, bod=2v7
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=12external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external, bod=4v3
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=8external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=enable,chip=167,clock=737external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=921external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=921external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=110external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=110external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=147external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=147external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=184external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx61
# LTO=disable, TimerClockSource=default, chip=861, clock=8internal, eesave=aenable, bod=1v8
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=pll, chip=461, clock=16pll, eesave=disable, bod=1v8
# PLL Timer source not compatible with Servo library and I can't add individual jobs for each library due to Travis CI's 200 job limit, so I can only do a single compilation to check this board configuration
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=pll,chip=461,clock=16pll,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=lowpll, clock=20external, bod=2v7
# PLL Timer source not compatible with Servo library and I can't add individual jobs for each library due to Travis CI's 200 job limit, so I can only do a single compilation to check this board configuration
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=lowpll,chip=861,clock=20external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=4v3
# The libraries have already been tested with F_CPU of 16000000UL in the clock=16pll job so only a single compilation is necessary to test the clock=16external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=16external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=12external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=enable,TimerClockSource=default,chip=861,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# chip=261, clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=261,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=6external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
# Servo library only supported at 1MHz, 8MHz and 16MHz on tiny261/461/861 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61:LTO=disable,TimerClockSource=default,chip=861,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx61opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, TimerClockSource=default, chip=861, clock=8internal, eesave=aenable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=pll, chip=461, clock=16pll, eesave=disable, bod=1v8
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=pll,chip=461,clock=16pll,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# TimerClockSource=lowpll, clock=20external, bod=2v7
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=lowpll,chip=861,clock=20external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=4v3
# The libraries have already been tested with F_CPU of 16000000UL in the clock=16pll job so only a single compilation is necessary to test the clock=16external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=16external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=12external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=enable,TimerClockSource=default,chip=861,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx61opti:LTO=disable,TimerClockSource=default,chip=861,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx41
# LTO=disable, chip=841, clock=8internal, eesave=aenable, bod=1v8, bodact=disabled, bodpd=disabled, pinmapping=anew,wiremode=amaster, wiremode=both
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=20external, eesave=disable, bod=2v7, bodact=enabled, bodpd=enabled, pinmapping=old
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=20external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled,pinmapping=old,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=16external, bod=4v3, bodact=sampled, bodpd=sampled, wiremode=both
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=16external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# LTO=enable, clock=12external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=enable,chip=841,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# chip=441, clock=8external, wiremode=amaster
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
# The Wire library can't be used in slave mode when the wiremode option is set to amaster and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=441,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=6external, wiremode=slave
# The Wire library can't be used in master mode when the wiremode option is set to slave and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=slave" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=4external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=4external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=512internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=512internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=256internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=256internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=128internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=128internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=64internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=64internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=32internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx41:LTO=disable,chip=841,clock=32internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# attinyx41opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# bootUART=UART0, LTO=disable, chip=841, clock=8internal, eesave=aenable, bod=1v8, bodact=disabled, bodpd=disabled, pinmapping=anew,wiremode=amaster, wiremode=amaster
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# bootUART=UART1, chip=441, clock=20external, eesave=disable, bod=2v7, bodact=enabled, bodpd=enabled, pinmapping=old, wiremode=slave
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART1,LTO=disable,chip=441,clock=20external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled,pinmapping=old,wiremode=slave" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=16external, bod=4v3, bodact=sampled, bodpd=sampled, wiremode=both
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=16external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled,pinmapping=anew,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# LTO=enable, clock=12external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=enable,chip=841,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=8internal5v
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=8internal5v,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=921external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=921external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=110external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=110external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=147external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=147external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx41opti:bootUART=UART0,LTO=disable,chip=841,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,pinmapping=anew,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
# attiny43
# LTO=disable, clock=8internal, eesave=aenable, bod=disable
# The Servo library is not compatible with ATtiny43 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny43:LTO=disable,clock=8internal,eesave=aenable,bod=disable,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal, eesave=disable, bod=1v8
# The Servo library is not compatible with ATtiny43 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny43:LTO=disable,clock=4internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal, bod=2v7
# The Servo library is not compatible with ATtiny43 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny43:LTO=disable,clock=1internal,eesave=aenable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, bod=4v3
# The Servo library is not compatible with ATtiny43 and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny43:LTO=enable,clock=8internal,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# attiny828
# LTO=disable, clock=8internal, eesave=aenable, bod=1v8, bodact=disabled, bodpd=disabled, wiremode=amaster
# The Wire library can't be used in slave mode when the wiremode option is set to amaster and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny828:LTO=disable,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal, eesave=disable, bod=2v7, bodact=enabled, bodpd=enabled, wiremode=slave
# The Wire library can't be used in master mode when the wiremode option is set to slave and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny828:LTO=disable,clock=1internal,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled,wiremode=slave" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=16external, bod=4v3, bodact=sampled, bodpd=sampled, wiremode=both
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny828:LTO=enable,clock=8internal,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# attiny828opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# LTO=disable, vcc=3v3, bod=1v8, bodact=disabled, bodpd=disabled, wiremode=amaster
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny828opti:LTO=disable,clock=8internal,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled,wiremode=amaster" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# vcc=5v, bod=2v7, bodact=enabled, bodpd=enabled, wiremode=slave
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny828opti:LTO=disable,clock=8internal5v,bod=2v7,neopixelport=portb,millis=enabled,bodact=enabled,bodpd=enabled,wiremode=slave" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, bod=4v3, bodact=sampled, bodpd=sampled, wiremode=both, clock=16external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny828opti:LTO=enable,clock=16external,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled,wiremode=both" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# attiny1634
# LTO=disable, clock=8internal, eesave=aenable, bod=1v8, bodact=disabled, bodpd=disabled
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, eesave=disable, bod=2v7, bodact=enabled, bodpd=enabled
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=12external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external, bod=4v3, bodact=sampled, bodpd=sampled
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=8external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=737external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=enable,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=143external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=143external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=6external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attiny1634:LTO=disable,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attiny1634opti
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
# bootUART=UART0, LTO=disable, clock=8internal, eesave=aenable, bod=1v8, bodact=disabled, bodpd=disabled
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# bootUART=UART1, clock=12external, eesave=disable, bod=2v7, bodact=enabled, bodpd=enabled
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART1,LTO=disable,clock=12external,eesave=disable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external, bod=4v3, bodact=sampled, bodpd=sampled
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=8external,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled,bodact=sampled,bodpd=sampled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=enable,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=921external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=921external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=110external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=110external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=147external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=147external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attiny1634opti:bootUART=UART0,LTO=disable,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,bodact=disabled,bodpd=disabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# attinyx313
# Some example sketches are too big to compile for these chips and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation for each board configuration
# LTO=disable, chip=4313, clock=8internal, eesave=aenable, bod=1v8, INITIALIZE_SECONDARY_TIMERS=0
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# chip=2313, clock=20external, eesave=disable, bod=1v8, INITIALIZE_SECONDARY_TIMERS=1
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=2313,clock=20external,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=1" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=16external, bod=2v7
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=12external, bod=4v3
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=8external
# The libraries have already been tested with F_CPU of 8000000UL in the clock=8internal job so only a single compilation is necessary to test the clock=8external option
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=8external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# LTO=enable, clock=6external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=enable,chip=4313,clock=6external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
# clock=4external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=4external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=1internal
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=1internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=4internal
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=4internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=5internal
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=5internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=737external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=737external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=92external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=92external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=11external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=11external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=14external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=14external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
# clock=184external
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx313:LTO=disable,chip=4313,clock=184external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled,INITIALIZE_SECONDARY_TIMERS=0" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
before_install:
# Formatting checks:
# Check for files starting with a blank line
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or \( -not -name '*.lst' -and -type f \) -print0 | xargs -0 -L1 bash -c 'head -1 "$0" | grep --binary-files=without-match --regexp="^$"; if [[ "$?" == "0" ]]; then echo "Blank line found at start of $0."; false; fi'
# Check for tabs
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or \( -not -name 'keywords.txt' -not -iname 'makefile*' -not -name '*.lst' -and -type f \) -exec grep --with-filename --line-number --binary-files=without-match --regexp=$'\t' '{}' \; -exec echo 'Tab found.' \; -exec false '{}' +
# Check for trailing whitespace
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or \( -not -name '*.lst' -and -type f \) -exec grep --with-filename --line-number --binary-files=without-match --regexp='[[:blank:]]$' '{}' \; -exec echo 'Trailing whitespace found.' \; -exec false '{}' +
# Check for non-Unix line endings
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or -type f -exec grep --files-with-matches --binary-files=without-match --regexp=$'\r$' '{}' \; -exec echo 'Non-Unix EOL detected.' \; -exec false '{}' +
# Check for blank lines at end of files
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or -path './avr/cores/MCUdude_corefiles' -prune -or -path './avr/bootloaders' -prune -or -type f -print0 | xargs -0 -L1 bash -c 'tail -1 "$0" | grep --binary-files=without-match --regexp="^$"; if [[ "$?" == "0" ]]; then echo "Blank line found at end of $0."; false; fi'
# Check for files that don't end in a newline (https://stackoverflow.com/a/25686825)
- find . -path './.git' -prune -or -path './avr/travis-ci' -prune -or \( -not -name '*.lst' -and -type f \) -print0 | xargs -0 -L1 bash -c 'if test "$(grep --files-with-matches --binary-files=without-match --max-count=1 --regexp='.*' "$0")" && test "$(tail --bytes=1 "$0")"; then echo "No new line at end of $0."; false; fi'
# Check for typos
- pip install codespell
- codespell --skip=*.lst,"${TRAVIS_BUILD_DIR}/.git","${TRAVIS_BUILD_DIR}/avr/travis-ci" --ignore-words="${TRAVIS_BUILD_DIR}/avr/travis-ci/etc/codespell-ignore-words-list.txt" "${TRAVIS_BUILD_DIR}"
# Install the script used to simplify use of Travis CI for testing Arduino projects
- source "${TRAVIS_BUILD_DIR}/avr/travis-ci/arduino-ci-script/arduino-ci-script.sh"
# These functions can be used to get verbose output for debugging the script
# set_script_verbosity can be set to values from 0 - 2 (verbosity off - maximum verbosity)
# - set_script_verbosity 2
# Setting set_verbose_output_during_compilation to true is the same as File > Preferences > Show verbose output during > compilation (check) in the Arduino IDE
#- set_verbose_output_during_compilation "true"
- set_application_folder "$APPLICATION_FOLDER"
- set_sketchbook_folder "$SKETCHBOOK_FOLDER"
# Check for board definition errors that don't affect compilation
- set_board_testing "true"
# Check for library issues that don't affect compilation
- set_library_testing "true"
# Install ATTinyCore from the repository
- install_package
# Check for common issues with the bundled libraries and their example sketches
- check_library_structure "${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" 1
# Check for common issues with library.properties files
- check_library_properties "${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" 1
# Install the Arduino IDE
- install_ide "$IDE_VERSION_LIST"
# Check for common issues with keywords.txt files (must be done after installing the IDE to check the reference links)
- check_keywords_txt "${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" 1
script:
# Verify every sketch in SKETCH_PATH using the environment variables set in the matrix
- build_sketch "$SKETCH_PATH" "$BOARD_ID" "$ALLOW_FAILURE" "$IDE_VERSION_LIST"
after_script:
# Determine user name and repository name from TRAVIS_REPO_SLUG so the configuration will automatically adjust to forks
- USER_NAME="$(echo "$TRAVIS_REPO_SLUG" | cut -d'/' -f 1)"
- REPOSITORY_NAME="$(echo "$TRAVIS_REPO_SLUG" | cut -d'/' -f 2)"
# Commit a report of the job results to a folder named with the build number in the MegaCore branch of the Travis-build-outputs repository
- publish_report_to_repository "$REPORT_GITHUB_TOKEN" "https://github.com/${USER_NAME}/CI-reports.git" "$REPOSITORY_NAME" "build_$(printf "%05d\n" "${TRAVIS_BUILD_NUMBER}")" "false"
# Print a tab separated report of all sketch verification results to the log
- display_report
notifications:
email:
on_success: always
on_failure: always
webhooks:
urls:
- https://www.travisbuddy.com/
on_success: never
on_failure: always