diff --git a/README.md b/README.md new file mode 100644 index 0000000..1102909 --- /dev/null +++ b/README.md @@ -0,0 +1,123 @@ +# Arduino Yocto Project + +This repository contains two Yocto layers designed to support Arduino hardware platforms: + +## Layers Overview + +### 1. `meta-arduino-bsp` +This layer provides Board Support Package (BSP) configurations for Arduino hardware platforms. It includes: +- Device tree overlays. +- Kernel module recipes for Arduino-supported peripherals. +- U-Boot configurations for Arduino boards. + +### 2. `meta-arduino-lmp` +This layer provides specific customizations targeting the Linux Micro Platform (LMP) distribution from Foundries.io (Qualcomm). It includes: +- Custom configurations for LMP. +- Recipes for integrating Arduino-specific features with LMP. + +## Getting Started [LmP Builds] + +1. Initialize and sync the Yocto manifest: + ```bash + repo init -u https://source.foundries.io/factories/arduino/lmp-manifest.git -m arduino.xml -b devel + repo sync -j1 --fail-fast + ``` +2. Build the Docker image for the Yocto environment: + ```bash + cd .repo/manifests + docker build -t yocto-lmp-v93 . + cd ../.. + ``` +3. Set up the Docker environment: + ```bash + docker run -it -u $UID -v $PWD:/workdir -w /workdir --name yocto-lmp yocto-lmp-v93 bash + ``` + +### Build mfgtools + +1. Configure the build environment for `mfgtool-files`: + ```bash + DISTRO=lmp-mfgtool MACHINE=portenta-x9 . setup-environment + echo "ACCEPT_FSL_EULA = \"1\"" >> conf/local.conf + echo "MFGTOOL_FLASH_IMAGE = \"lmp-devel-arduino-image\"" >> conf/local.conf + ``` +2. Build the `mfgtool-files`: + ```bash + bitbake mfgtool-files + ``` + +### Build the Image + +1. Configure the build environment for the image: + ```bash + DISTRO=lmp-base-xwayland MACHINE=portenta-x9 . setup-environment + echo "ACCEPT_FSL_EULA = \"1\"" >> conf/local.conf + ``` +2. Build the image: + ```bash + bitbake lmp-devel-arduino-image + ``` + +### Supported Images + +- `lmp-devel-arduino-image` +- `lmp-factory-image` + +## Getting Started [NXP Builds] + +1. Initialize and sync the Yocto manifest: + ```bash + repo init -u https://github.com/nxp-imx/imx-manifest.git -m imx-6.6.3-1.0.0.xml -b imx-linux-nanbield + repo sync -j1 --fail-fast + ``` +2. Clone this repository into the `sources` directory created by the manifest: + ```bash + cd sources + git clone https://github.com/Arduino/meta-arduino.git + cd meta-arduino && git checkout nanbield + ``` +3. Set up the Docker environment: + ```bash + docker run -it -u $UID -v $PWD:/workdir -w /workdir --name yocto-nxp arduino/yocto-lmp-v93 bash # First time only + docker start yocto-nxp # Every login, skip first time + cd ~/yocto/nxp && docker exec -it yocto-nxp bash # Every login, skip first time + ``` +4. Configure the build environment: + ```bash + MACHINE=portenta-x9 DISTRO=fsl-imx-xwayland EULA=yes source ./imx-setup-release.sh -b bld-xwayland # First time only + ``` +5. Add the layers to your `bblayers.conf` file: + ```bash + echo 'BBLAYERS += "${BSPDIR}/sources/meta-arduino/meta-arduino-bsp"' >> conf/bblayers.conf + ``` +6. Customize your `local.conf` file to optimize the build environment: + ```bash + BB_NUMBER_PARSE_THREADS = "4" + BB_NUMBER_THREADS = "4" + PARALLEL_MAKE = "-j 4" + ``` + +## Supported Boards + +- Portenta X8 +- Portenta X9 +- Raspberry Pi CM4 +- System Electronics Astrial + +## Building the Image + +Run the following commands to build an image: +```bash +source setup-environment +bitbake +``` + +Replace `` with the desired image recipe, such as `arduino-console-image`. + +## Contributing + +Contributions are welcome! Please submit pull requests or open issues for any bugs or feature requests. + +## License + +This project is licensed under the [GPL-2.0+](https://www.gnu.org/licenses/old-licenses/gpl-2.0.html). diff --git a/meta-arduino-bsp/conf/machine/imx8mp-astrial.conf b/meta-arduino-bsp/conf/machine/imx8mp-astrial.conf new file mode 100644 index 0000000..f9a354b --- /dev/null +++ b/meta-arduino-bsp/conf/machine/imx8mp-astrial.conf @@ -0,0 +1,39 @@ +#@TYPE: Machine +#@NAME: System Electronics Astrial +#@SOC: i.MX8MP +#@DESCRIPTION: Machine configuration for System Electronics Astrial i.MX 8M Plus board with LPDDR4 +#@MAINTAINER: Arduino + +require conf/machine/imx8mp-lpddr4-evk.conf + +MACHINEOVERRIDES .= ":imx8mp-lpddr4-evk" + +# Override the variables you want to change here +IMX_DEFAULT_BSP = "nxp" +PREFERRED_PROVIDER:virtual/kernel = "linux-imx_6.6" +KBUILD_DEFCONFIG:imx8mp-astrial = "" +KERNEL_DEVICETREE = "" +KERNEL_DEVICETREE:remove:imx8mp-astrial = " freescale/imx8mp-evk-root.dtb" +PREFERRED_PROVIDER:virtual/dtb ?= "arduino-device-tree" + +# Include custom device tree for linux kernel +MACHINE_EXTRA_RRECOMMENDS += "arduino-device-tree" + +# Add additional out of tree modules +MACHINE_EXTRA_RRECOMMENDS += "kernel-module-nxp-wlan" + +# Firmware NXP IW612 chipset +PREFERRED_RPROVIDER_linux-firmware-nxpiw612-sdio = "firmware-nxp-wifi" +MACHINE_EXTRA_RRECOMMENDS += "firmware-nxp-wifi-nxpiw612-sdio firmware-nxp-wifi" + +# Hailo PCIE driver +MACHINE_EXTRA_RRECOMMENDS += "hailo-pcie-driver" + +# Additional specific packages +MACHINE_EXTRA_RRECOMMENDS += "lmbench" + +# Custom wks file +WKS_FILE:mx8mp-nxp-bsp = "imx-imx-boot-singlepart.wks.in" + +# @TODO: below seems to be ignored +SERIAL_CONSOLES = "115200;ttymxc0" diff --git a/meta-arduino-bsp/conf/machine/portenta-x8.conf b/meta-arduino-bsp/conf/machine/portenta-x8.conf index ed20464..05a1efc 100644 --- a/meta-arduino-bsp/conf/machine/portenta-x8.conf +++ b/meta-arduino-bsp/conf/machine/portenta-x8.conf @@ -9,22 +9,24 @@ require conf/machine/imx8mm-lpddr4-evk.conf MACHINEOVERRIDES .= ":imx8mm-lpddr4-evk" # Override the variables you want to change here -UBOOT_CONFIG_BASENAME = "portenta-x8" -UBOOT_DTB_NAME = "portenta-x8.dtb" - IMX_DEFAULT_BSP = "nxp" PREFERRED_PROVIDER:virtual/kernel = "linux-imx_6.6" -#KERNEL_DEFCONFIG = "portenta_x8_defconfig" -KBUILD_DEFCONFIG:portenta-x8 = "portenta_x8_defconfig" +KBUILD_DEFCONFIG:portenta-x8 = "" KERNEL_DEVICETREE = "" KERNEL_DEVICETREE:remove:portenta-x8 = " freescale/imx8mm-evk.dtb" PREFERRED_PROVIDER:virtual/dtb ?= "arduino-device-tree" +# Tweak machine features +MACHINE_FEATURES:remove:portenta-x8 = " \ + nxp8987-sdio \ + nxpwifi-all-sdio \ +" + # Include custom device tree for linux kernel MACHINE_EXTRA_RRECOMMENDS += "arduino-device-tree" # Add additional firmware, mostly support for Murata 1DX WiFi / Bluetooth solution -MACHINE_FIRMWARE:append = " linux-firmware linux-firmware-cyw-fmac-fw linux-firmware-cyw-fmac-nvram linux-firmware-cyw-bt-patch" +MACHINE_FIRMWARE:append = " linux-firmware-cyw-fmac-fw linux-firmware-cyw-fmac-nvram linux-firmware-cyw-bt-patch" # Added X8H7 solution based on ext. STM32 mcu MACHINE_FIRMWARE:append = " linux-firmware-arduino-portenta-x8-stm32h7" @@ -36,13 +38,13 @@ MACHINE_EXTRA_RRECOMMENDS += "anx7625" MACHINE_EXTRA_RRECOMMENDS += "x8h7" # Add extra kernel modules needed for Max carrier board -MACHINE_EXTRA_RRECOMMENDS += "bq24195 cs42l52" +#MACHINE_EXTRA_RRECOMMENDS += "bq24195 cs42l52" # Add mipi-csi cmos sensors drivers -MACHINE_EXTRA_RRECOMMENDS += "ov5647-mipi imx219 imx477 imx708" +#MACHINE_EXTRA_RRECOMMENDS += "ov5647-mipi imx219 imx477 imx708" # Add mipi-dsi panels and touch screen controllers drivers -MACHINE_EXTRA_RRECOMMENDS += "panel-sitronix-st7701 panel-jadard-ek79202d atmel-mxt-ts" +#MACHINE_EXTRA_RRECOMMENDS += "panel-sitronix-st7701 panel-jadard-ek79202d atmel-mxt-ts" # Add neural external pcie modules drivers MACHINE_EXTRA_RRECOMMENDS += "google-gasket-driver akida-pcie-driver hailo-pcie-driver" @@ -57,7 +59,17 @@ CORE_IMAGE_BASE_INSTALL:remove:portenta-x8 = " \ linux-firmware-bcm43430 \ " +# Remove default linux-firmware and nxp-wifi firmware that are not needed +# and very big in size +CORE_IMAGE_BASE_INSTALL:remove:portenta-x8 = " \ + firmware-nxp-wifi \ + linux-firmware \ +" + KERNEL_MODULE_AUTOLOAD:portenta-x8:append = "anx7625 i2c-dev spidev" +# Custom wks file +WKS_FILE:mx8mm-nxp-bsp = "imx-imx-boot-singlepart.wks.in" + # @TODO: below seems to be ignored SERIAL_CONSOLES = "115200;ttymxc2" diff --git a/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.bb b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.bb index ef0db74..a84d44d 100644 --- a/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.bb +++ b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.bb @@ -16,7 +16,7 @@ include recipes-bsp/device-tree/arduino-device-tree.inc # ignoring everything else do_move_dts_files() { bbdebug 2 "Moving dts files for MACHINE=${MACHINE}" - cp ${WORKDIR}/${MACHINE}/*.dts ${WORKDIR}/ + cp ${WORKDIR}/${MACHINE}/*.dts* ${WORKDIR}/ if [ -d "${WORKDIR}/${MACHINE}/overlays" ]; then cp ${WORKDIR}/${MACHINE}/overlays/*.dts ${WORKDIR}/ fi diff --git a/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.inc b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.inc index 2fb89ef..2eb4865 100644 --- a/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.inc +++ b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree.inc @@ -89,12 +89,22 @@ SRC_URI:append:portenta-x9 = " \ " COMPATIBLE_MACHINE:portenta-x9 = ".*" -# Raspberry Pi Section -# Opta Gateway +# System Electronics Astrial supporting ??? +DTB_OVERLAYS:append:imx8mp-astrial = " \ +" + +# System Electronics Astrial root devicetree +SRC_URI:append:imx8mp-astrial = " \ + file://imx8mp-astrial/imx8mp-astrial.dts \ + ${DTB_OVERLAYS} \ +" +COMPATIBLE_MACHINE:imx8mp-astrial = ".*" + +# Raspberry Pi CM4 supporting Opta Gateway DTB_OVERLAYS:append:raspberrypi4-64 = " \ file://raspberrypi4-64/overlays/ov_opta_gateway.dts \ " -# Raspberry Pi root devicetree +# Raspberry Pi CM4 root devicetree SRC_URI:append:raspberrypi4-64 = " \ file://raspberrypi4-64/bcm2711-rpi-cm4-merged.dts \ file://raspberrypi4-64/bcm2711-rpi-cm4-optagateway.dts \ diff --git a/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree/imx8mp-astrial/imx8mp-astrial.dts b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree/imx8mp-astrial/imx8mp-astrial.dts new file mode 100644 index 0000000..d1d2c45 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/device-tree/arduino-device-tree/imx8mp-astrial/imx8mp-astrial.dts @@ -0,0 +1,1076 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "System Electronics i.MX 8M Plus Astrial board"; + compatible = "fsl,imx8mp-astrial", "fsl,imx8mp-evk", "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 1 0x00000000>, + <0x1 0x40000000 1 0x00000000>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&dsp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&aud2htx { + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev1: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev2: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + eee-broken-1000t; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + /* Enable level translator for i2c2 */ + nxp,i2c-lt-enable; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + imx219_1: imx219_mipi@10 { + compatible = "sony,imx219"; + reg = <0x10>; + pinctrl-0 = <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <1>; + /* Camera_GPIO (CAM_GPIO) >> GPIO1_5 */ + /* serves both cameras according to RPi CM4IO */ + /* reset-gpios => for standard imx219 driver */ + /* rst-gpios => for nxp imx219 driver */ + /* reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; */ + /* rst-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; */ + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + + status = "okay"; + + port { + imx219_mipi_1_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + /* We could do 4 but Raspberry Cam v2 only handles 2 */ + data-lanes = <1 2>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* I2C on expansion connector J22. */ +&i2c5 { + clock-frequency = <100000>; /* Lower clock speed for external bus. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + status = "disabled"; /* can1 pins conflict with i2c5 */ + + /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: + * LOW: CAN1 (default, pull-down) + * HIGH: I2C5 + * You need to set it to high to enable I2C5 (for example, add gpio-hog + * in pca6416 node). + */ +}; + +&i2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + status = "okay"; + + imx219_0: imx219_mipi@10 { + compatible = "sony,imx219"; + reg = <0x10>; + pinctrl-0 = <&pinctrl_csi0_rst>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + /* Camera_GPIO (CAM_GPIO) >> GPIO1_5 */ + /* serves both cameras according to RPi CM4IO */ + /* rst-gpios => for nxp imx219 driver */ + /* reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; */ + /* rst-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; */ + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + + status = "okay"; + + port { + imx219_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + clock-lanes = <0>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmi_blk_ctrl { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; + + thres-low = <1 2>; /* (FIFO * 1 / 2) */ + thres-high = <3 4>; /* (FIFO * 3 / 4) */ +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + host-wake-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&uart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune = <0xe>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vboost-level = <5>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "none"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + usb1_connector: usb1-connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-B"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vref-tune = <0xb>; + status = "disabled"; +}; + +&usb3_1 { + status = "disabled"; +}; + +/* @TODO: overlaps with PCIE pins if you follow RPi CM4IO schematics */ +&usb_dwc3_1 { + /*vbus-supply = <®_usb_vbus>;*/ + dr_mode = "host"; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { /* Sd Card 1 */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + broken-cd; + no-1-8-v; + status = "disabled"; +}; + +&usdhc2 { /* Sd Card 2 */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + broken-cd; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010 + /* + * M.2 pin20 & pin21 need to be set to 11 for 88W9098 to select the + * default Reference Clock Frequency + */ + /*MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4*/ /* Used as UART3_RXD */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_usb0: usb0-extcongrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c2 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ /* PCIE_CLKREQ_N */ + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x40 /* PCIE_RST_N */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 /* PCIE_WAKE_N */ + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; + + pinctrl_csi0_rst: csi0-rstgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&vpu_v4l2 { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + port { + mipi_csi0_ep: endpoint { + remote-endpoint = <&imx219_mipi_0_ep>; + data-lanes = <2>; + csis-hs-settle = <16>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + reg = <1>; + mipi_csi1_ep: endpoint { + remote-endpoint = <&imx219_mipi_1_ep>; + data-lanes = <2>; + csis-hs-settle = <16>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&cameradev { + status = "okay"; +}; + +&isi_0 { + status = "disabled"; + + cap_device { + status = "disabled"; + }; + + m2m_device { + status = "disabled"; + }; +}; + +&isi_1 { + status = "disabled"; + + cap_device { + status = "okay"; + }; +}; + +&isp_0 { + status = "okay"; +}; + +&isp_1 { + status = "okay"; +}; + +&dewarp { + status = "okay"; +}; diff --git a/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart1.patch b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart1.patch new file mode 100644 index 0000000..2b156d4 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart1.patch @@ -0,0 +1,30 @@ +From 66574a3900280de6d4b013c13d0402ea6a24d82f Mon Sep 17 00:00:00 2001 +From: Mauro Salvini +Date: Thu, 15 Feb 2024 11:20:19 +0100 +Subject: [PATCH] imx8mp_bl31_setup: add UART1 to peripherals permission list + +UART1 is the debug serial on the System Electronics Astrial board +--- + plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c +index 348f900..e536737 100644 +--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c ++++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c +@@ -73,6 +73,7 @@ static const struct imx_rdc_cfg rdc[] = { + + + /* peripherals domain permission */ ++ RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + RDC_PDAPn(RDC_PDAP_WDOG1, D0R | D0W), + RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R), +@@ -135,6 +136,7 @@ static const struct imx_rdc_cfg rdc[] = { + RDC_MDAn(RDC_MDA_M7, DID1), + + /* peripherals domain permission */ ++ RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + RDC_PDAPn(RDC_PDAP_WDOG1, D0R | D0W), + RDC_PDAPn(RDC_PDAP_RDC, D0R | D0W | D1R), diff --git a/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart3.patch b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart3.patch new file mode 100644 index 0000000..4331f75 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf/console-uart3.patch @@ -0,0 +1,13 @@ +diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +index 8702d5160..e68102ee1 100644 +--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c ++++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +@@ -108,7 +108,7 @@ static const struct imx_rdc_cfg rdc[] = { + RDC_MDAn(RDC_MDA_M4, DID1), + + /* peripherals domain permission */ +- RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), ++ RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W), + diff --git a/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf_%.bbappend b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf_%.bbappend index ae1d840..3011d94 100644 --- a/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf_%.bbappend +++ b/meta-arduino-bsp/recipes-bsp/imx-atf/imx-atf_%.bbappend @@ -2,8 +2,18 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" # FIXME: We should return INVALID here but currently only i.MX8M has support to override the UART # base address in source code. +ATF_BOOT_UART_BASE:portenta-x8 ?= "0x30880000" ATF_BOOT_UART_BASE:portenta-x9 ?= "0x42570000" +ATF_BOOT_UART_BASE:imx8mp-astrial ?= "0x30860000" + +SRC_URI:append:portenta-x8 = " \ + file://console-uart3.patch \ +" SRC_URI:append:portenta-x9 = " \ file://console-lpuart3.patch \ " + +SRC_URI:append:astrial-imx8mp = " \ + file://console-uart1.patch \ +" diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/Makefile b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/Makefile similarity index 98% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/Makefile rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/Makefile index 862b707..3942216 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/Makefile +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/Makefile @@ -1071,31 +1071,14 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ - imx8mp-dhcom-pdk2.dtb \ imx8mp-ddr4-evk.dtb \ imx8mp-evk.dtb \ - imx8mp-icore-mx8mp-edimm2.2.dtb \ - imx8mp-msc-sm2s.dtb \ - imx8mp-phyboard-pollux-rdk.dtb \ - imx8mp-venice.dtb \ - imx8mp-venice-gw74xx.dtb \ - imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ - imx8mq-librem5-r4.dtb \ - portenta-x8.dtb + imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx95-19x19-evk.dtb \ - imx95-19x19-titan.dtb \ imx93-11x11-evk.dtb \ - imx93-11x11-evk-pmic-pf0900.dtb \ - imx93-14x14-evk.dtb \ - imx93-9x9-qsb.dtb \ - imx93-9x9-qsb-ontat-wvga-panel.dtb \ - imx91p-11x11-evk.dtb \ - imx91p-9x9-qsb-ontat-wvga-panel.dtb \ - imx91p-9x9-qsb-spinand.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/ddr4_timing.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/ddr4_timing.c new file mode 100644 index 0000000..3e3cc01 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/ddr4_timing.c @@ -0,0 +1,1311 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0xaa }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0xc30118 }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, +#endif + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc0030188 }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xc500501 }, + { 0x3d4000e0, 0x280400 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x1010 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x1618361a }, + { 0x3d400104, 0x50626 }, + { 0x3d400108, 0x80b0610 }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0xc04060d }, + { 0x3d400114, 0x8080504 }, + { 0x3d40011c, 0x808 }, + { 0x3d400120, 0x6060d0a }, + { 0x3d400124, 0x2050c }, + { 0x3d40012c, 0x160b010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x61a8 }, + { 0x3d400190, 0x391820b }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0x110b }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x1f }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400204, 0x3f0505 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x14141400 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x4040403 }, + { 0x3d400218, 0x4040404 }, + { 0x3d40021c, 0xf04 }, +#else + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, +#endif + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000618 }, + { 0x3d400244, 0x1323 }, + { 0x3d400250, 0x00001a05 }, + { 0x3d400254, 0x1f }, + { 0x3d40025c, 0x10000010 }, + { 0x3d400264, 0x100000ff }, + { 0x3d40026c, 0x100002ff }, + { 0x3d40036c, 0x0 }, + { 0x3d400400, 0x100 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x40005e }, + { 0x3d4020dc, 0x40501 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x4030205 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x3030d04 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1005010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2df }, + { 0x1015f, 0x2df }, + { 0x1105f, 0x2df }, + { 0x1115f, 0x2df }, + { 0x1205f, 0x2df }, + { 0x1215f, 0x2df }, + { 0x1305f, 0x2df }, + { 0x1315f, 0x2df }, + { 0x11005f, 0x2df }, + { 0x11015f, 0x2df }, + { 0x11105f, 0x2df }, + { 0x11115f, 0x2df }, + { 0x11205f, 0x2df }, + { 0x11215f, 0x2df }, + { 0x11305f, 0x2df }, + { 0x11315f, 0x2df }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x7 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x1204d, 0x1a }, + { 0x1214d, 0x1a }, + { 0x1304d, 0x1a }, + { 0x1314d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x11204d, 0x1a }, + { 0x11214d, 0x1a }, + { 0x11304d, 0x1a }, + { 0x11314d, 0x1a }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x43, 0xe7 }, + { 0x1043, 0xe7 }, + { 0x2043, 0xe7 }, + { 0x3043, 0xe7 }, + { 0x4043, 0xe7 }, + { 0x5043, 0xe7 }, + { 0x6043, 0xe7 }, + { 0x7043, 0xe7 }, + { 0x8043, 0xe7 }, + { 0x9043, 0xe7 }, + { 0x20018, 0x5 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x248 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x12043, 0x5b1 }, + { 0x12143, 0x5b1 }, + { 0x13043, 0x5b1 }, + { 0x13143, 0x5b1 }, + { 0x1200b2, 0x248 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x112043, 0x5b1 }, + { 0x112143, 0x5b1 }, + { 0x113043, 0x5b1 }, + { 0x113143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xc50 }, + { 0x54030, 0x501 }, + { 0x54031, 0x28 }, + { 0x54032, 0x400 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x1010 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x501 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0xc50 }, + { 0x54030, 0x501 }, + { 0x54031, 0x28 }, + { 0x54032, 0x400 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x1010 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x104 }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x448 }, + { 0x900a9, 0x109 }, + { 0x900aa, 0xf }, + { 0x900ab, 0x7c0 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0x47 }, + { 0x900ae, 0x630 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x8 }, + { 0x900b1, 0x618 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0xe0 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x0 }, + { 0x900b7, 0x7c8 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x8 }, + { 0x900ba, 0x8140 }, + { 0x900bb, 0x10c }, + { 0x900bc, 0x0 }, + { 0x900bd, 0x478 }, + { 0x900be, 0x109 }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2a }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 1066, }, +}; + +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} +#endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial-u-boot.dtsi b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial-u-boot.dtsi new file mode 100644 index 0000000..697c142 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial-u-boot.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + * Copyright 2024 Koan Software + */ +#include "imx8mp-sec-def.h" + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + mcu_rdc { + compatible = "imx8m,mcu_rdc"; + /* rdc config when MCU starts + * master + * SDMA3p --> domain 1 + * SDMA3b --> domian 1 + * SDMA3_SPBA2 --> domian 1 + * peripheral: + * SAI3 --> Only Domian 1 can access + * UART4 --> Only Domian 1 can access + * GPT1 --> Only Domian 1 can access + * SDMA3 --> Only Domian 1 can access + * I2C3 --> Only Domian 1 can access + * memory: + * TCM --> Only Domian 1 can access (0x7E0000~0x81FFFF) + * DDR --> Only Domian 1 can access (0x80000000~0x81000000) + * end. + */ + start-config = < + RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0 + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + /* rdc config when MCU stops + * memory: + * TCM --> domain 0/1 can access (0x7E0000~0x81FFFF) + * DDR --> domain 0/1 can access (0x80000000~0x81000000) + * end. + */ + stop-config = < + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + }; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + /*sd-uhs-sdr104;*/ + /*sd-uhs-ddr50;*/ + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +ðphy0 { + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&flexspi { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&usb_dwc3_0 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usb_dwc3_1 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial.dts b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial.dts new file mode 100644 index 0000000..c093803 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial.dts @@ -0,0 +1,681 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright 2024 Koan Software + */ + +/dts-v1/; + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "System Electronics i.MX 8M Plus Astrial board"; + compatible = "fsl,imx8mp-astrial", "fsl,imx8mp"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + /* Keeping EN_1V8_H8 low >> disabling Hailo */ + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + eee-broken-1000t; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + status = "disabled"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "disabled"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + vpcie-supply = <®_pcie0>; + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + /delete-property/ dmas; + /delete-property/ dmas-names; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune = <0xe>; + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vboost-level = <5>; + fsl,phy-comp-dis-tune = <7>; + fsl,pcs-tx-deemph-3p5db = <0x21>; + fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "none"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + usb1_connector: usb1-connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-B"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <3>; + fsl,phy-tx-vref-tune = <0xb>; + status = "disabled"; +}; + +&usb3_1 { + status = "disabled"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "disabled"; +}; + +&usdhc2 { /* Sd Card */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + broken-cd; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x142 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x142 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ /* PCIE_CLKREQ_N */ + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x40 /* PCIE_RST_N */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 /* PCIE_WAKE_N */ + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usb0: usb0extcongrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing.c new file mode 100644 index 0000000..8aad88d --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing.c @@ -0,0 +1,2048 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x124f800 }, + { 0x3d400064, 0x4900a8 }, + { 0x3d400070, 0x1027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc0030495 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0xc40024 }, +#else + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a017c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, +#endif + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, +#endif + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400100, 0x1618141a }, + { 0x3d400104, 0x504a6 }, + { 0x3d40010c, 0x909000 }, + { 0x3d400110, 0xb04060b }, + { 0x3d400114, 0x2030909 }, + { 0x3d400118, 0x1010006 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20500 }, + { 0x3d400134, 0xb100002 }, + { 0x3d400138, 0xad }, + { 0x3d400144, 0x78003c }, + { 0x3d400180, 0x2580012 }, + { 0x3d400184, 0x1e0493e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4938208 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1308 }, +#else + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x184 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, +#endif + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400108, 0x60c1514 }, + { 0x3d400200, 0x18 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400250, 0x1f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x90003ff }, + { 0x3d40026c, 0x20003ff }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x1000e00 }, + { 0x3d400498, 0x3ff0000 }, + { 0x3d40049c, 0x1000e00 }, + { 0x3d4004a0, 0x3ff0000 }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, +#else + { 0x3d400108, 0x9121c1c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400200, 0x13 }, + { 0x3d40020c, 0x13131300 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x68040404 }, +#else + { 0x3d400200, 0x18 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, +#endif + { 0x3d40021c, 0xf07 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0026 }, +#endif + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x27 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, +#else + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, +#endif + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0xa }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x200c5, 0xa }, +#else + { 0x200c5, 0x18 }, +#endif + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x20008, 0x258 }, +#else + { 0x20008, 0x3e8 }, +#endif + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, +#endif + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, +#endif + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, +#else + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, +#endif + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, +#endif + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 1D */ + .drate = 2400, +#else + /* P0 4000mts 1D */ + .drate = 4000, +#endif + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 2D */ + .drate = 2400, +#else + /* P0 4000mts 2D */ + .drate = 4000, +#endif + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + .fsp_table = { 2400, 400, 100, }, +#else + .fsp_table = { 4000, 400, 100, }, +#endif +}; + +#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0, 0x3ffffff); + ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff); + ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff); + ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff); + ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff); + ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff); + ddrc_inline_ecc_scrub(0x8000000, 0xbffffff); + ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff); + ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff); + ddrc_inline_ecc_scrub(0xc000000, 0xfffffff); + ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff); + ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff); + ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff); + ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff); + ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff); + ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff); + ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff); + ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff); + ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff); + ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff); + ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff); + ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); +} +#endif +#endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing_ndm.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing_ndm.c new file mode 100644 index 0000000..4765618 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_lpddr4_timing_ndm.c @@ -0,0 +1,1853 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x186a000 }, + { 0x3d400064, 0x610130 }, + { 0x3d400070, 0x1027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc003061c }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1a201b22 }, + { 0x3d400104, 0x60633 }, + { 0x3d40010c, 0xc0c000 }, + { 0x3d400110, 0xf04080f }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x136 }, + { 0x3d400144, 0xa00050 }, + { 0x3d400180, 0x3200018 }, + { 0x3d400184, 0x28061a8 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0026 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x27 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0xa }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_spl.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_spl.c new file mode 100644 index 0000000..362751e --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp-astrial_spl.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ +#ifdef CONFIG_SPL_BOOTROM_SUPPORT + return BOOT_DEVICE_BOOTROM; +#else + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ +#if defined(CONFIG_IMX8M_LPDDR4) && !defined(CONFIG_IMX8M_VDD_SOC_850MV) + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +#endif +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + +#ifdef CONFIG_IMX8M_LPDDR4 + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ +#ifdef CONFIG_IMX8M_VDD_SOC_850MV + /* set DVS0 to 0.85v for special case*/ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); +#else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); +#elif defined(CONFIG_IMX8M_DDR4) + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Set NVCC_DRAM to 1.2v for DDR4 */ + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.c new file mode 100644 index 0000000..23362fc --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.c @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2024 Koan Software + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../freescale/common/tcpc.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define __SYSTEM_ELECTRONICS_BOARD_VERSION__ "01.00" + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS + +static void setup_gpmi_nand(void) +{ + init_nand_clk(); +} +#endif + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .images = fw_images, +}; + +u8 num_image_type_guids = ARRAY_SIZE(fw_images); +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(0); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK + int rc; + phys_addr_t ecc_start = 0x120000000; + size_t ecc_size = 0x20000000; + + rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc reserved-memory node.\n"); + return rc; + } +#else + int rc; + phys_addr_t ecc0_start = 0xb0000000; + phys_addr_t ecc1_start = 0x130000000; + phys_addr_t ecc2_start = 0x1b0000000; + size_t ecc_size = 0x10000000; + + rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc0 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc1 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc2 reserved-memory node.\n"); + return rc; + } +#endif +#endif + + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else + return -EINVAL; +} + +/* Port2 is the power supply, port 1 does not support power */ +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, +}; + +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) +#define USB_TYPEC_EN IMX_GPIO_NR(2, 20) + +static iomux_v3_cfg_t ss_mux_gpio[] = { + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 0); + else + gpio_direction_output(USB_TYPEC_SEL, 1); +} + +static int setup_typec(void) +{ + int ret; + struct gpio_desc per_12v_desc; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + printf("Power supply on USB2\n"); + + /* Enable PER 12V, any check before it? */ + ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); + if (ret) { + printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); + if (ret) { + printf("%s request per_12v failed ret = %d\n", __func__, ret); + return -EIO; + } + + /* Enable PER 12V regulator */ + dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + + debug("tcpc_init port 1\n"); + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + gpio_request(USB_TYPEC_EN, "typec_en"); + gpio_direction_output(USB_TYPEC_EN, 0); + + ret = tcpc_init(&port1, port1_config, &ss_mux_select); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + return ret; + } + + return ret; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +#define USB_PHY_CTRL6 0xF0058 + +#define HSIO_GPR_BASE (0x32F10000U) +#define HSIO_GPR_REG_0 (HSIO_GPR_BASE) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) + + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(index); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + /* enable usb clock via hsio gpr */ + RegData = readl(HSIO_GPR_REG_0); + RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; + writel(RegData, HSIO_GPR_REG_0); + + /* USB3.0 PHY signal fsel for 100M ref */ + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData = (RegData & 0xfffff81f) | (0x2a<<5); + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL6); + RegData &=~0x1; + writel(RegData, dwc3->base + USB_PHY_CTRL6); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +#define USB2_PWR_EN IMX_GPIO_NR(1, 14) +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0 && init == USB_INIT_DEVICE) { + imx8m_usb_power(index, true); +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port1); + if (ret) + return ret; +#endif + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port1); +#endif + return ret; + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + imx8m_usb_power(index, false); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port1); +#endif + } + + return ret; +} + +#ifdef CONFIG_USB_TCPC +/* Not used so far */ +int board_typec_get_mode(int index) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (index == 0) { + tcpc_setup_ufp_mode(&port1); + + ret = tcpc_get_cc_status(&port1, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; + } else { + return USB_INIT_HOST; + } +} +#endif +#endif + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} + +#if CONFIG_IS_ENABLED(NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (IS_ENABLED(CONFIG_FEC_MXC)) { + setup_fec(); + } + + if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) { + setup_eqos(); + } + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "ASTRIAL"); + env_set("board_rev", "iMX8MP"); +#endif + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: System Electronics iMX8MP ASTRIAL (version " __SYSTEM_ELECTRONICS_BOARD_VERSION__ ")\n"); + return 0; +} +#endif + +#ifdef CONFIG_SPL_DISPLAY_PRINT +void spl_display_print(void) +{ + checkboard(); +} +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_SPL_MMC +#define UBOOT_RAW_SECTOR_OFFSET 0x40 +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + u32 boot_dev = spl_boot_device(); + switch (boot_dev) { + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; + default: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + } +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.h b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.h new file mode 100644 index 0000000..1dbac12 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Copyright 2024 KOAN + */ + +#ifndef __IMX8MP_EVK_H +#define __IMX8MP_EVK_H + +#include +#include +#include +#include "imx_env.h" + +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include +#else +#define BOOTENV +#endif + +#define JH_ROOT_DTB "imx8mp-evk-root.dtb" + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_root_dtb=" JH_ROOT_DTB "\0" \ + "jh_mmcboot=setenv fdtfile ${jh_root_dtb};" \ + "setenv jh_clk clk_ignore_unused mem=1920MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1920MB; run netboot; \0 " + +#define SR_IR_V2_COMMAND \ + "nodes=/busfreq /power-domains /soc@0/caam-sm@100000 /soc@0/bus@30000000/caam_secvio /soc@0/bus@30000000/caam-snvs@30370000 /soc@0/bus@30800000/flexspi_nand@30bb0000 /soc@0/bus@32c00000/mipi_dsi@32e60000 /soc@0/bus@32c00000/lcd-controller@32e80000 /soc@0/bus@32c00000/blk-ctl@32ec0000 /soc@0/bus@30800000/i2c@30a20000/pca9450@25 /soc@0/bus@30800000/i2c@30a30000/adv7535@3d /soc@0/bus@30800000/i2c@30a30000/tcpc@50 /wdt-reboot /mcu_rdc /soc@0/bus@30800000/ethernet@30bf0000 /dsi-host /rm67199_panel /cbtl04gp /binman /vpu_g1@38300000 /vpu_g2@38310000 /vpu_vc8000e@38320000 /vpu_v4l2 /gpu3d@38000000 /gpu2d@38008000 /vipsi@38500000 /mix_gpu_ml \0" \ + "sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000;"\ + "fdt addr ${fdt_addr_r};"\ + "fdt set /soc@0/usb@32f10100/usb@38100000 compatible snps,dwc3;" \ + "fdt set /soc@0/usb@32f10108/usb@38200000 compatible snps,dwc3;" \ + "for i in ${nodes}; do fdt rm ${i}; done \0" + +#define CFG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" + + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),64m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CFG_EXTRA_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ + "splashimage=0x50000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x4000000;"\ + "nand read ${fdt_addr_r} 0x9000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr_r}" + +#else +#define CFG_EXTRA_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + SR_IR_V2_COMMAND \ + BOOTENV \ + "prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bsp_script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x50000000\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "swapper=echo Test storage device ...; " \ + "if test -e mmc 1:1 ${fdtfile}; then " \ + "echo Swap to microSD; " \ + "setenv mmcdev 1; " \ + "setenv mmcroot '/dev/mmcblk1p2 rootwait rw'; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" +#endif + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + + +/* Totally 8GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GB */ +#define PHYS_SDRAM_2 0x140000000 +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ +#else +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ +#endif + +#define CFG_MXC_UART_BASE UART1_BASE_ADDR + +#define CFG_SYS_NAND_BASE 0x20000000 + +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK +#define CFG_SYS_FSL_USDHC_NUM 1 +#else +#define CFG_SYS_FSL_USDHC_NUM 2 +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8mp_evk_android.h" +#endif + +#endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_defconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_defconfig new file mode 100644 index 0000000..31c7a33 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_defconfig @@ -0,0 +1,214 @@ +CONFIG_ENV_IMPORT_FDT=y +CONFIG_ENV_FDT_PATH="/config/environment" +# Below is the default configuration for the NXP i.MX8MP EVK board +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_IMX_BOOTAUX=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +# CONFIG_USB_TCPC is not set +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x96dff0 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_BOOTCOMMAND="run sr_ir_v2_cmd;run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_REMAKE_ELF=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_LED=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_IMX8M_BLK_CTRL=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_ADV7535=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_SPL_RSA=y +CONFIG_SHA384=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_AUTHENTICATE=y +CONFIG_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_TEE=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_HAVE_CAPSULE_UPDATE=y +CONFIG_FIT_SIGNATURE=y diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_inline_ecc_defconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_inline_ecc_defconfig new file mode 100644 index 0000000..2c4448f --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_inline_ecc_defconfig @@ -0,0 +1,197 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_IMX_BOOTAUX=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_REMAKE_ELF=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x96dff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_FIXUP=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_IMX8M_BLK_CTRL=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_ndm_defconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_ndm_defconfig new file mode 100644 index 0000000..c691741 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imx8mp_astrial_ndm_defconfig @@ -0,0 +1,202 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_IMX_BOOTAUX=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40400000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_REMAKE_ELF=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96e000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x96dff0 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_LED=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_IMX8M_BLK_CTRL=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_ADV7535=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_IMX8M_VDD_SOC_850MV=y +CONFIG_IMX8M_LPDDR4_FREQ0_3200MTS=y diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imximage-8mp-lpddr4.cfg b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000..6dedf17 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/imx8mp-astrial/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/Makefile b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/Makefile new file mode 100644 index 0000000..11d6933 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/Makefile @@ -0,0 +1,1410 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb +dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb +dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb +dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb + +dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos4210-universal_c210.dtb \ + exynos4210-trats.dtb \ + exynos4412-trats2.dtb \ + exynos4412-odroid.dtb + +dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb +dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb + +dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb + +dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \ + exynos5250-snow.dtb \ + exynos5250-spring.dtb \ + exynos5250-smdk5250.dtb \ + exynos5420-smdk5420.dtb \ + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb +dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb +dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb + +dtb-$(CONFIG_ARCH_APPLE) += \ + t8103-j274.dtb \ + t8103-j293.dtb \ + t8103-j313.dtb \ + t8103-j456.dtb \ + t8103-j457.dtb + +dtb-$(CONFIG_ARCH_DAVINCI) += \ + da850-evm.dtb \ + da850-lcdk.dtb \ + da850-lego-ev3.dtb + +dtb-$(CONFIG_ARCH_KIRKWOOD) += \ + kirkwood-atl-sbx81lifkw.dtb \ + kirkwood-atl-sbx81lifxcat.dtb \ + kirkwood-blackarmor-nas220.dtb \ + kirkwood-d2net.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-is2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-net2big.dtb \ + kirkwood-ns2.dtb \ + kirkwood-ns2lite.dtb \ + kirkwood-ns2max.dtb \ + kirkwood-ns2mini.dtb \ + kirkwood-nsa310s.dtb \ + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ + kirkwood-pogo_e02.dtb \ + kirkwood-pogoplug-series-4.dtb \ + kirkwood-sheevaplug.dtb + +dtb-$(CONFIG_MACH_S900) += \ + bubblegum_96.dtb +dtb-$(CONFIG_MACH_S700) += \ + s700-cubieboard7.dtb + +dtb-$(CONFIG_ROCKCHIP_PX30) += \ + px30-evb.dtb \ + px30-firefly.dtb \ + px30-engicam-px30-core-ctouch2.dtb \ + px30-engicam-px30-core-ctouch2-of10.dtb \ + px30-engicam-px30-core-edimm2.2.dtb \ + rk3326-odroid-go2.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3036) += \ + rk3036-sdk.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3066) += \ + rk3066a-mk808.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3128) += \ + rk3128-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3188) += \ + rk3188-radxarock.dtb + +dtb-$(CONFIG_ROCKCHIP_RK322X) += \ + rk3229-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3288) += \ + rk3288-evb.dtb \ + rk3288-firefly.dtb \ + rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ + rk3288-popmetal.dtb \ + rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ + rk3288-tinker.dtb \ + rk3288-tinker-s.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-minnie.dtb \ + rk3288-veyron-speedy.dtb \ + rk3288-vyasa.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + rk3308-evb.dtb \ + rk3308-roc-cc.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3368) += \ + rk3368-lion-haikou.dtb \ + rk3368-sheep.dtb \ + rk3368-geekbox.dtb \ + rk3368-px5-evb.dtb \ + +dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-evb.dtb \ + rk3399-eaidk-610.dtb \ + rk3399-ficus.dtb \ + rk3399-firefly.dtb \ + rk3399-gru-bob.dtb \ + rk3399-gru-kevin.dtb \ + rk3399-khadas-edge.dtb \ + rk3399-khadas-edge-captain.dtb \ + rk3399-khadas-edge-v.dtb \ + rk3399-leez-p710.dtb \ + rk3399-nanopc-t4.dtb \ + rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-m4b.dtb \ + rk3399-nanopi-neo4.dtb \ + rk3399-nanopi-r4s.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-pinephone-pro.dtb \ + rk3399-puma-haikou.dtb \ + rk3399-roc-pc.dtb \ + rk3399-roc-pc-mezzanine.dtb \ + rk3399-rock-pi-4a.dtb \ + rk3399-rock-pi-4b.dtb \ + rk3399-rock-pi-4c.dtb \ + rk3399-rock960.dtb \ + rk3399-rockpro64.dtb \ + rk3399pro-rock-pi-n10.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-evb.dtb \ + rk3566-radxa-cm3-io.dtb \ + rk3568-rock-3a.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588-edgeble-neu6a-io.dtb \ + rk3588-rock-5b.dtb + +dtb-$(CONFIG_ROCKCHIP_RV1108) += \ + rv1108-elgin-r1.dtb \ + rv1108-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RV1126) += \ + rv1126-edgeble-neu2-io.dtb + +dtb-$(CONFIG_ARCH_S5P4418) += \ + s5p4418-nanopi2.dtb + +dtb-$(CONFIG_ARCH_MESON) += \ + meson-axg-s400.dtb \ + meson-axg-jethome-jethub-j100.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-odroidc2.dtb \ + meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-p200.dtb \ + meson-gxbb-p201.dtb \ + meson-gxl-s805x-libretech-ac.dtb \ + meson-gxl-s905d-libretech-pc.dtb \ + meson-gxl-s905w-jethome-jethub-j80.dtb \ + meson-gxl-s905x-khadas-vim.dtb \ + meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-libretech-cc-v2.dtb \ + meson-gxl-s905x-p212.dtb \ + meson-gxm-khadas-vim2.dtb \ + meson-gxm-s912-libretech-pc.dtb \ + meson-gxm-wetek-core2.dtb \ + meson-g12a-radxa-zero.dtb \ + meson-g12a-sei510.dtb \ + meson-g12a-u200.dtb \ + meson-g12b-a311d-khadas-vim3.dtb \ + meson-g12b-gtking.dtb \ + meson-g12b-gtking-pro.dtb \ + meson-g12b-gsking-x.dtb \ + meson-g12b-odroid-go-ultra.dtb \ + meson-g12b-odroid-n2.dtb \ + meson-g12b-odroid-n2l.dtb \ + meson-g12b-odroid-n2-plus.dtb \ + meson-sm1-bananapi-m5.dtb \ + meson-sm1-khadas-vim3l.dtb \ + meson-sm1-odroid-c4.dtb \ + meson-sm1-odroid-hc4.dtb \ + meson-sm1-sei610.dtb +dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb \ + tegra20-colibri.dtb \ + tegra30-apalis.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu.dtb \ + tegra30-colibri.dtb \ + tegra30-tec-ng.dtb \ + tegra114-dalmore.dtb \ + tegra124-apalis.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-cei-tk1-som.dtb \ + tegra124-venice2.dtb \ + tegra186-p2771-0000-000.dtb \ + tegra186-p2771-0000-500.dtb \ + tegra210-p2371-0000.dtb \ + tegra210-p2371-2180.dtb \ + tegra210-p2571.dtb \ + tegra210-p3450-0000.dtb + +ifdef CONFIG_ARMADA_32BIT +ifdef CONFIG_ARMADA_375 +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-375-db.dtb +else +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-385-atl-x530.dtb \ + armada-385-atl-x530DP.dtb \ + armada-385-db-88f6820-amc.dtb \ + armada-385-synology-ds116.dtb \ + armada-385-thecus-n2350.dtb \ + armada-385-turris-omnia.dtb \ + armada-388-clearfog.dtb \ + armada-388-gp.dtb \ + armada-388-helios4.dtb \ + armada-38x-controlcenterdc.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ + armada-xp-db-xc3-24g4xg.dtb \ + armada-xp-gp.dtb \ + armada-xp-maxbcm.dtb \ + armada-xp-synology-ds414.dtb \ + armada-xp-theadorable.dtb +endif +else +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-3720-db.dtb \ + armada-3720-espressobin.dtb \ + armada-3720-turris-mox.dtb \ + armada-3720-eDPU.dtb \ + armada-3720-uDPU.dtb \ + armada-7040-db-nand.dtb \ + armada-7040-db.dtb \ + armada-8040-clearfog-gt-8k.dtb \ + armada-8040-db.dtb \ + armada-8040-mcbin.dtb \ + armada-8040-puzzle-m801.dtb \ + cn9130-db-A.dtb \ + cn9130-db-B.dtb \ + cn9131-db-A.dtb \ + cn9131-db-B.dtb \ + cn9132-db-A.dtb \ + cn9132-db-B.dtb \ + cn9130-crb-A.dtb \ + cn9130-crb-B.dtb \ + ac5-98dx35xx-rd.dtb +endif + +dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ + uniphier-ld11-global.dtb \ + uniphier-ld11-ref.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ + uniphier-ld20-akebi96.dtb \ + uniphier-ld20-global.dtb \ + uniphier-ld20-ref.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ + uniphier-ld4-ref.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_LD6B) += \ + uniphier-ld6b-ref.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_PRO4) += \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_PRO5) += \ + uniphier-pro5-4kbox.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ + uniphier-pxs3-ref.dtb +dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ + uniphier-sld8-ref.dtb + +dtb-$(CONFIG_ARCH_ZYNQ) += \ + bitmain-antminer-s9.dtb \ + zynq-cc108.dtb \ + zynq-cse-nand.dtb \ + zynq-cse-nor.dtb \ + zynq-cse-qspi-single.dtb \ + zynq-dlc20-rev1.0.dtb \ + zynq-microzed.dtb \ + zynq-minized.dtb \ + zynq-picozed.dtb \ + zynq-syzygy-hub.dtb \ + zynq-topic-miami.dtb \ + zynq-topic-miamilite.dtb \ + zynq-topic-miamiplus.dtb \ + zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ + zynq-zc770-xm011-x16.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ + zynq-zed.dtb \ + zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ + zynq-zybo.dtb \ + zynq-zybo-z7.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += \ + avnet-ultra96-rev1.dtb \ + zynqmp-a2197-revA.dtb \ + zynqmp-dlc21-revA.dtb \ + zynqmp-e-a2197-00-revA.dtb \ + zynqmp-g-a2197-00-revA.dtb \ + zynqmp-m-a2197-01-revA.dtb \ + zynqmp-m-a2197-02-revA.dtb \ + zynqmp-m-a2197-03-revA.dtb \ + zynqmp-p-a2197-00-revA.dtb \ + zynqmp-mini.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ + zynqmp-mini-nand.dtb \ + zynqmp-mini-qspi.dtb \ + zynqmp-sm-k24-revA.dtb \ + zynqmp-smk-k24-revA.dtb \ + zynqmp-sm-k26-revA.dtb \ + zynqmp-smk-k26-revA.dtb \ + zynqmp-sck-kr-g-revA.dtbo \ + zynqmp-sck-kr-g-revB.dtbo \ + zynqmp-sck-kv-g-revA.dtbo \ + zynqmp-sck-kv-g-revB.dtbo \ + zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ + zynqmp-zcu100-revC.dtb \ + zynqmp-zcu102-revA.dtb \ + zynqmp-zcu102-revB.dtb \ + zynqmp-zcu102-rev1.0.dtb \ + zynqmp-zcu102-rev1.1.dtb \ + zynqmp-zcu104-revA.dtb \ + zynqmp-zcu104-revC.dtb \ + zynqmp-zcu106-revA.dtb \ + zynqmp-zcu106-rev1.0.dtb \ + zynqmp-zcu111-revA.dtb \ + zynqmp-zcu1275-revA.dtb \ + zynqmp-zcu1275-revB.dtb \ + zynqmp-zcu1285-revA.dtb \ + zynqmp-zcu208-revA.dtb \ + zynqmp-zcu216-revA.dtb \ + zynqmp-zc1232-revA.dtb \ + zynqmp-zc1254-revA.dtb \ + zynqmp-zc1751-xm015-dc1.dtb \ + zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm017-dc3.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ + zynqmp-zc1751-xm019-dc5.dtb +dtb-$(CONFIG_ARCH_VERSAL) += \ + versal-mini.dtb \ + versal-mini-emmc0.dtb \ + versal-mini-emmc1.dtb \ + versal-mini-ospi-single.dtb \ + versal-mini-qspi-single.dtb \ + xilinx-versal-virt.dtb +dtb-$(CONFIG_ARCH_VERSAL_NET) += \ + versal-net-mini.dtb \ + xilinx-versal-net-virt.dtb +dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ + zynqmp-r5.dtb +dtb-$(CONFIG_AM33XX) += \ + am335x-baltos.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ + am335x-brppt1-mmc.dtb \ + am335x-brxre1.dtb \ + am335x-brsmarc1.dtb \ + am335x-draco.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-bonegreen.dtb \ + am335x-bonegreen-wireless.dtb \ + am335x-icev2.dtb \ + am335x-pocketbeagle.dtb \ + am335x-pxm50.dtb \ + am335x-rut.dtb \ + am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ + am335x-shc.dtb \ + am335x-pdu001.dtb \ + am335x-chiliboard.dtb \ + am335x-sl50.dtb \ + am335x-base0033.dtb \ + am335x-guardian.dtb \ + am335x-wega-rdk.dtb \ + am335x-regor-rdk.dtb +dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ + am43x-epos-evm.dtb \ + am437x-idk-evm.dtb \ + am4372-generic.dtb \ + am437x-cm-t43.dtb +dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb +dtb-$(CONFIG_TI816X) += dm8168-evm.dtb +dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb + +dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex_socdk.dtb \ + socfpga_arria5_secu1.dtb \ + socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3_270_2.dtb \ + socfpga_arria10_chameleonv3_270_3.dtb \ + socfpga_arria10_chameleonv3_480_2.dtb \ + socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_mcvevk.dtb \ + socfpga_cyclone5_is1.dtb \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_dbm_soc1.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de1_soc.dtb \ + socfpga_cyclone5_de10_nano.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sr1500.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_n5x_socdk.dtb \ + socfpga_stratix10_socdk.dtb + +dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ + dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb +dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ + am57xx-beagle-x15-revc.dtb \ + am5729-beagleboneai.dtb \ + am574x-idk.dtb \ + am572x-idk.dtb \ + am571x-idk.dtb +dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb + +dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ + ls1021a-qds-lpuart.dtb \ + ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ + ls1021a-iot-duart.dtb ls1021a-tsn.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb + +dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ + fsl-ls2080a-rdb.dtb \ + fsl-ls2081a-rdb.dtb \ + fsl-ls2088a-rdb-qspi.dtb \ + fsl-ls1088a-rdb.dtb \ + fsl-ls1088a-qds.dtb \ + fsl-ls1088a-qds-21-x.dtb \ + fsl-ls1088a-qds-29-x.dtb \ + fsl-ls1028a-rdb.dtb \ + fsl-ls1028a-qds-duart.dtb \ + fsl-ls1028a-qds-lpuart.dtb \ + fsl-lx2160a-rdb.dtb \ + fsl-lx2160a-qds.dtb \ + fsl-lx2160a-qds-3-x-x.dtb \ + fsl-lx2160a-qds-3-11-x.dtb \ + fsl-lx2160a-qds-7-x-x.dtb \ + fsl-lx2160a-qds-7-11-x.dtb \ + fsl-lx2160a-qds-19-x-x.dtb \ + fsl-lx2160a-qds-19-11-x.dtb \ + fsl-lx2160a-qds-20-x-x.dtb \ + fsl-lx2160a-qds-20-11-x.dtb \ + fsl-lx2160a-qds-13-x-x.dtb \ + fsl-lx2160a-qds-14-x-x.dtb \ + fsl-lx2162a-qds.dtb\ + fsl-lx2162a-qds-17-x.dtb\ + fsl-lx2162a-qds-18-x.dtb\ + fsl-lx2162a-qds-20-x.dtb +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ + fsl-ls1043a-qds-lpuart.dtb \ + fsl-ls1043a-rdb.dtb \ + fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ + fsl-ls1046a-rdb.dtb \ + fsl-ls1046a-frwy.dtb \ + fsl-ls1012a-qds.dtb \ + fsl-ls1012a-rdb.dtb \ + fsl-ls1012a-2g5rdb.dtb \ + fsl-ls1012a-frdm.dtb \ + fsl-ls1012a-frwy.dtb +dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ + fsl-ls1028a-kontron-sl28-var1.dtb \ + fsl-ls1028a-kontron-sl28-var2.dtb \ + fsl-ls1028a-kontron-sl28-var3.dtb \ + fsl-ls1028a-kontron-sl28-var4.dtb \ + +dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb + +dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb +dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb +dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb +dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb + +dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb + +dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ + stm32429i-eval.dtb \ + stm32f469-disco.dtb + +dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ + stm32f769-disco.dtb \ + stm32746g-eval.dtb +dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ + stm32h743i-eval.dtb \ + stm32h750i-art-pi.dtb + +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet-3f.dtb \ + sun4i-a10-inet-3w.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-ampe-a76.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-86vs.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31-mixtile-loftq.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-ainol-aw1.dtb \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-m5.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-primo73.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb \ + sun7i-a20-yones-toptech-bd1078.dtb +dtb-$(CONFIG_MACH_SUN8I_A23) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb +dtb-$(CONFIG_MACH_SUN8I_A33) += \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb +dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb +dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb +dtb-$(CONFIG_MACH_SUN8I_R40) += \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb +dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-bananapi-m2-plus.dtb \ + sun50i-h5-emlid-neutis-n5-devboard.dtb \ + sun50i-h5-libretech-all-h3-cc.dtb \ + sun50i-h5-libretech-all-h3-it.dtb \ + sun50i-h5-libretech-all-h5-cc.dtb \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-nanopi-r1s-h5.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ + sun50i-h5-orangepi-pc2.dtb \ + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb +dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ + sun50i-h6-orangepi-3.dtb \ + sun50i-h6-orangepi-lite2.dtb \ + sun50i-h6-orangepi-one-plus.dtb \ + sun50i-h6-pine-h64.dtb \ + sun50i-h6-pine-h64-model-b.dtb \ + sun50i-h6-tanix-tx6.dtb \ + sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_MACH_SUN50I_H616) += \ + sun50i-h616-orangepi-zero2.dtb \ + sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-amarula-relic.dtb \ + sun50i-a64-bananapi-m64.dtb \ + sun50i-a64-nanopi-a64.dtb \ + sun50i-a64-oceanic-5205-5inmfd.dtb \ + sun50i-a64-olinuxino.dtb \ + sun50i-a64-olinuxino-emmc.dtb \ + sun50i-a64-orangepi-win.dtb \ + sun50i-a64-pine64-lts.dtb \ + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ + sun50i-a64-pinephone-1.0.dtb \ + sun50i-a64-pinephone-1.1.dtb \ + sun50i-a64-pinephone-1.2.dtb \ + sun50i-a64-pinetab.dtb \ + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb +dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb \ + sun9i-a80-cx-a99.dtb + +dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \ + vf610-twr.dtb \ + vf610-pcm052.dtb \ + vf610-bk4r1.dtb + +dtb-$(CONFIG_MX23) += \ + imx23-evk.dtb + +dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ + imx23-olinuxino.dtb + +dtb-$(CONFIG_MX28) += \ + imx28-evk.dtb \ + imx28-xea.dtb + +dtb-$(CONFIG_MX51) += \ + imx51-babbage.dtb + +dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ + imx53-qsb.dtb \ + imx53-kp.dtb \ + imx53-m53menlo.dtb \ + imx53-usbarmory.dtb + +ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) +dtb-y += \ + imx6dl-aristainetos2c_7.dtb \ + imx6dl-aristainetos2c_cslb_7.dtb \ + imx6dl-brppt2.dtb \ + imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ + imx6dl-dhcom-pdk2.dtb \ + imx6dl-dhcom-picoitx.dts \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-gw551x.dtb \ + imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ + imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ + imx6dl-icore-rqs.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ + imx6dl-mamoj.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-pico.dtb \ + imx6dl-udoo.dtb \ + imx6dl-riotboard.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-wandboard-revd1.dtb \ + imx6s-dhcom-drc02.dtb + +endif + +ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL)$(CONFIG_MX6QP),) +dtb-y += \ + imx6q-apalis-eval.dtb \ + imx6q-bosch-acc.dtb \ + imx6q-cm-fx6.dtb \ + imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ + imx6q-dhcom-pdk2.dtb \ + imx6q-display5.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw54xx.dtb \ + imx6q-gw551x.dtb \ + imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ + imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-icore.dtb \ + imx6q-icore-mipi.dtb \ + imx6q-icore-rqs.dtb \ + imx6q-kp.dtb \ + imx6q-logicpd.dtb \ + imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ + imx6q-mccmon6.dtb\ + imx6q-nitrogen6x.dtb \ + imx6q-novena.dtb \ + imx6q-pico.dtb \ + imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-udoo.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb \ + imx6q-tbs2910.dtb \ + imx6q-wandboard-revd1.dtb \ + imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ + imx6qp-sabresd.dtb \ + imx6qp-wandboard-revd1.dtb \ + +endif + +dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb + +dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \ + imx6sll-lpddr2-val.dtb \ + imx6sll-lpddr3-val.dtb \ + imx6sll-lpddr3-val-ecspi.dtb + +dtb-$(CONFIG_MX6SX) += \ + imx6sx-14x14-val.dtb \ + imx6sx-17x17-val.dtb \ + imx6sx-17x17-val-ecspi.dtb \ + imx6sx-17x17-val-gpmi-weim.dtb \ + imx6sx-19x19-val.dtb \ + imx6sx-19x19-val-ecspi.dtb \ + imx6sx-19x19-val-gpmi-weim.dtb \ + imx6sx-sabreauto.dtb \ + imx6sx-sdb.dtb \ + imx6sx-sdb-emmc.dtb \ + imx6sx-softing-vining-2000.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb + +dtb-$(CONFIG_MX6UL) += \ + imx6ul-geam.dtb \ + imx6ul-isiot-emmc.dtb \ + imx6ul-isiot-nand.dtb \ + imx6ul-opos6uldev.dtb \ + imx6ul-14x14-ddr3-val.dtb \ + imx6ul-14x14-ddr3-val-emmc.dtb \ + imx6ul-14x14-ddr3-val-gpmi-weim.dtb \ + imx6ul-14x14-lpddr2-val.dtb \ + imx6ul-14x14-evk.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ + imx6ul-9x9-evk.dtb \ + imx6ul-liteboard.dtb \ + imx6ul-phytec-segin-ff-rdk-nand.dtb \ + imx6ul-pico-hobbit.dtb \ + imx6ul-pico-pi.dtb \ + imx6ul-kontron-bl.dtb \ + imx6ull-kontron-bl.dtb + +dtb-$(CONFIG_MX6ULL) += \ + imx6ull-14x14-ddr3-val.dtb \ + imx6ull-14x14-ddr3-val-epdc.dtb \ + imx6ull-14x14-ddr3-val-emmc.dtb \ + imx6ull-14x14-ddr3-val-gpmi-weim.dtb \ + imx6ull-14x14-ddr3-val-tsc.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ull-9x9-evk.dtb \ + imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-eval-v3.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-seeed-npi-imx6ull-dev-board.dtb \ + imx6ull-phytec-segin-ff-rdk-emmc.dtb \ + imx6ull-dart-6ul.dtb \ + imx6ull-somlabs-visionsom.dtb \ + imx6ulz-bsh-smm-m2.dtb \ + imx6ulz-14x14-evk.dtb \ + imx6ulz-14x14-evk-emmc.dtb \ + imx6ulz-14x14-evk-gpmi-weim.dtb + +dtb-$(CONFIG_ARCH_MX6) += \ + imx6q-apalis-eval.dtb \ + imx6dl-colibri-eval-v3.dtb + +dtb-$(CONFIG_O4_IMX_NANO) += \ + o4-imx-nano.dtb + +dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \ + ev-imx280-nano-x-mb.dtb + +dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ + imx7d-sdb-qspi.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-reva.dtb \ + imx7-cm.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ + imx7d-colibri-eval-v3.dtb \ + imx7s-warp.dtb \ + imx7d-meerkat96.dtb \ + imx7d-pico-pi.dtb \ + imx7d-pico-hobbit.dtb \ + imx7d-smegw01.dtb \ + imx7d-12x12-lpddr3-val.dtb \ + imx7d-12x12-lpddr3-val-ecspi.dtb \ + imx7d-12x12-lpddr3-val-qspi.dtb \ + imx7d-12x12-ddr3-val.dtb \ + imx7d-19x19-ddr3-val.dtb \ + imx7d-19x19-lpddr2-val.dtb \ + imx7d-19x19-lpddr3-val.dtb + +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ + imx7ulp-10x10-val.dtb \ + imx7ulp-14x14-val.dtb \ + imx7ulp-evk.dtb \ + imx7ulp-evk-emmc.dtb \ + imx7ulp-evk-qspi.dtb + +dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb + +dtb-$(CONFIG_ARCH_IMX8) += \ + fsl-imx8qm-apalis.dtb \ + fsl-imx8qm-mek.dtb \ + fsl-imx8qm-ddr4-val.dtb \ + fsl-imx8qm-lpddr4-val.dtb \ + fsl-imx8qm-mek-cockpit-a53.dtb \ + fsl-imx8qm-mek-cockpit-a72.dtb \ + fsl-imx8qm-mek-xen.dtb \ + imx8qm-cgtqmx8.dtb \ + imx8qm-rom7720-a1.dtb \ + fsl-imx8qxp-ai_ml.dtb \ + fsl-imx8qxp-colibri.dtb \ + fsl-imx8qxp-mek.dtb \ + fsl-imx8qxp-lpddr4-val.dtb \ + fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \ + fsl-imx8qxp-17x17-val.dtb \ + fsl-imx8dx-17x17-val.dtb \ + fsl-imx8dx-mek.dtb \ + fsl-imx8dxl-phantom-mek.dtb \ + fsl-imx8dxl-evk.dtb \ + fsl-imx8dxl-evk-lcdif.dtb \ + fsl-imx8dxl-ddr3l-evk.dtb \ + imx8-deneb.dtb \ + imx8-giedi.dtb + +dtb-$(CONFIG_ARCH_IMX8ULP) += \ + imx8ulp-evk.dtb \ + imx8ulp-evk-i3c.dtb \ + imx8ulp-9x9-evk.dtb \ + imx8ulp-9x9-evk-i3c.dtb \ + imx8ulp-watch.dtb + +dtb-$(CONFIG_ARCH_IMX8M) += \ + imx8mm-evk.dtb + +dtb-$(CONFIG_ARCH_IMX9) += \ + imx95-19x19-evk.dtb \ + imx95-19x19-titan.dtb \ + imx93-11x11-evk.dtb \ + imx93-11x11-evk-pmic-pf0900.dtb \ + imx93-14x14-evk.dtb \ + imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dtb \ + imx91p-11x11-evk.dtb \ + imx91p-9x9-qsb-ontat-wvga-panel.dtb \ + imx91p-9x9-qsb-spinand.dtb + +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ + imxrt1020-evk.dtb \ + imxrt1170-evk.dtb \ + +dtb-$(CONFIG_RCAR_GEN2) += \ + r8a7790-lager-u-boot.dtb \ + r8a7790-stout-u-boot.dtb \ + r8a7791-koelsch-u-boot.dtb \ + r8a7791-porter-u-boot.dtb \ + r8a7792-blanche-u-boot.dtb \ + r8a7793-gose-u-boot.dtb \ + r8a7794-alt-u-boot.dtb \ + r8a7794-silk-u-boot.dtb + +dtb-$(CONFIG_RCAR_GEN3) += \ + r8a774a1-beacon-rzg2m-kit.dtb \ + r8a774b1-beacon-rzg2n-kit.dtb \ + r8a774e1-beacon-rzg2h-kit.dtb \ + r8a774a1-hihope-rzg2m-u-boot.dtb \ + r8a774b1-hihope-rzg2n-u-boot.dtb \ + r8a774c0-ek874-u-boot.dtb \ + r8a774e1-hihope-rzg2h-u-boot.dtb \ + r8a77950-ulcb-u-boot.dtb \ + r8a77950-salvator-x-u-boot.dtb \ + r8a77960-ulcb-u-boot.dtb \ + r8a77960-salvator-x-u-boot.dtb \ + r8a77965-ulcb-u-boot.dtb \ + r8a77965-salvator-x-u-boot.dtb \ + r8a77970-eagle-u-boot.dtb \ + r8a77980-condor-u-boot.dtb \ + r8a77990-ebisu-u-boot.dtb \ + r8a77995-draak-u-boot.dtb \ + r8a779a0-falcon-u-boot.dtb + +ifdef CONFIG_RCAR_GEN3 +DTC_FLAGS += -R 4 -p 0x1000 +endif + +dtb-$(CONFIG_RZA1) += \ + r7s72100-gr-peach-u-boot.dtb + +dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb \ + keystone-k2g-generic.dtb \ + keystone-k2g-ice.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb + +dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb + +dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb + +dtb-$(CONFIG_TARGET_MEESC) += at91sam9263ek.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ + at91sam9260ek.dtb \ + at91sam9g20ek.dtb \ + at91sam9g20ek_2mmc.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb + +dtb-$(CONFIG_TARGET_PM9G45) += at91sam9m10g45ek.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ + at91sam9g15ek.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb + +dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb + +dtb-$(CONFIG_TARGET_SAM9X60_CURIOSITY) += at91-sam9x60_curiosity.dtb + +dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb + +dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \ + at91sam9g25-gardena-smart-gateway.dtb + +dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb + +dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb + +dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ + logicpd-som-lv-35xx-devkit.dtb \ + logicpd-som-lv-37xx-devkit.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit.dtb + +dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ + omap3-evm-37xx.dtb \ + omap3-evm.dtb + +dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ + omap3-beagle-xm-ab.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle.dtb + +dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb + +dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \ + omap3-igep0020.dtb + +dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \ + omap4-panda.dtb \ + omap4-panda-es.dtb + +dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ + omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb + +dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ + omap5-uevm.dtb + +dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ + at91-sama7g5ek.dtb + +dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ + at91-sama5d2_ptc_ek.dtb + +dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ + at91-sama5d2_xplained.dtb + +dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ + at91-sama5d27_som1_ek.dtb \ + at91-sama5d27_giantboard.dtb + +dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \ + at91-sama5d27_wlsom1_ek.dtb + +dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ + at91-sama5d2_icp.dtb + +dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb + +dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ + at91-sama5d3_xplained.dtb + +dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ + at91-sama5d4ek.dtb + +dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ + at91-sama5d4_xplained.dtb + +dtb-$(CONFIG_TARGET_VINCO) += \ + at91-vinco.dtb + +dtb-$(CONFIG_ARCH_BCM283X) += \ + bcm2835-rpi-a.dtb \ + bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-b-plus.dtb \ + bcm2835-rpi-b-rev2.dtb \ + bcm2835-rpi-cm1-io1.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb\ + bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2711-rpi-4-b.dtb + +dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb + +dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb + +dtb-$(CONFIG_BCM47622) += \ + bcm947622.dtb +dtb-$(CONFIG_BCM4908) += \ + bcm94908.dtb +dtb-$(CONFIG_BCM4912) += \ + bcm94912.dtb +dtb-$(CONFIG_BCM63138) += \ + bcm963138.dtb +dtb-$(CONFIG_BCM63146) += \ + bcm963146.dtb +dtb-$(CONFIG_BCM63148) += \ + bcm963148.dtb +dtb-$(CONFIG_BCM63158) += \ + bcm963158.dtb +dtb-$(CONFIG_BCM63178) += \ + bcm963178.dtb +dtb-$(CONFIG_BCM6756) += \ + bcm96756.dtb +dtb-$(CONFIG_BCM6813) += \ + bcm96813.dtb +dtb-$(CONFIG_BCM6846) += \ + bcm96846.dtb +dtb-$(CONFIG_BCM6855) += \ + bcm96855.dtb \ + bcm96753ref.dtb +dtb-$(CONFIG_BCM6856) += \ + bcm96856.dtb \ + bcm968360bg.dtb +dtb-$(CONFIG_BCM6858) += \ + bcm96858.dtb \ + bcm968580xref.dtb +dtb-$(CONFIG_BCM6878) += \ + bcm96878.dtb + +dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb +dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb + +dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb + +dtb-$(CONFIG_STM32MP13x) += \ + stm32mp135f-dk.dtb + +dtb-$(CONFIG_STM32MP15x) += \ + stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ + stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ + stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp15xx-dhcom-drc02.dtb \ + stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx.dtb \ + stm32mp15xx-dhcor-avenger96.dtb \ + stm32mp15xx-dhcor-drc-compact.dtb \ + stm32mp15xx-dhcor-testbench.dtb + +dtb-$(CONFIG_SOC_K3_AM654) += \ + k3-am654-base-board.dtb \ + k3-am654-r5-base-board.dtb \ + k3-am65-iot2050-spl.dtb \ + k3-am6528-iot2050-basic.dtb \ + k3-am6528-iot2050-basic-pg2.dtb \ + k3-am6548-iot2050-advanced.dtb \ + k3-am6548-iot2050-advanced-pg2.dtb +dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ + k3-j721e-r5-common-proc-board.dtb \ + k3-j7200-common-proc-board.dtb \ + k3-j7200-r5-common-proc-board.dtb \ + k3-j721e-sk.dtb \ + k3-j721e-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\ + k3-am68-sk-r5-base-board.dtb\ + k3-j721s2-common-proc-board.dtb\ + k3-j721s2-r5-common-proc-board.dtb +dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ + k3-am642-r5-evm.dtb \ + k3-am642-sk.dtb \ + k3-am642-r5-sk.dtb + +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ + k3-am625-r5-sk.dtb + +dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \ + k3-am62a7-r5-sk.dtb + +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7622-rfb.dtb \ + mt7623a-unielec-u7623-02-emmc.dtb \ + mt7622-bananapi-bpi-r64.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb \ + mt7981-rfb.dtb \ + mt7981-emmc-rfb.dtb \ + mt7981-sd-rfb.dtb \ + mt7986a-rfb.dtb \ + mt7986b-rfb.dtb \ + mt7986a-sd-rfb.dtb \ + mt7986b-sd-rfb.dtb \ + mt7986a-emmc-rfb.dtb \ + mt7986b-emmc-rfb.dtb \ + mt8183-pumpkin.dtb \ + mt8512-bm1-emmc.dtb \ + mt8516-pumpkin.dtb \ + mt8518-ap1-emmc.dtb + +dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb +dtb-$(CONFIG_ARCH_NPCM8XX) += nuvoton-npcm845-evb.dtb +dtb-$(CONFIG_XEN) += xenguest-arm64.dtb + +dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb +dtb-$(CONFIG_ARCH_OCTEONTX2) += octeontx.dtb + +dtb-$(CONFIG_TARGET_GE_BX50V3) += \ + imx6q-bx50v3.dtb \ + imx6q-b850v3.dtb \ + imx6q-b650v3.dtb \ + imx6q-b450v3.dtb + +dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb +dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb + +# TODO(Linus Walleij ): Should us a single vexpress +# Kconfig option to build all of these. See examples above. +dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASE_FVP) += fvp-base-revc.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_BASER_FVP) += arm_fvp.dtb +dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb + +dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb + +dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb + +dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb + +dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts + +dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \ + imx8mm-cl-iot-gate-ied.dtbo \ + imx8mm-cl-iot-gate-ied-adc0.dtbo \ + imx8mm-cl-iot-gate-ied-adc1.dtbo \ + imx8mm-cl-iot-gate-ied-can0.dtbo \ + imx8mm-cl-iot-gate-ied-can1.dtbo \ + imx8mm-cl-iot-gate-ied-tpm0.dtbo \ + imx8mm-cl-iot-gate-ied-tpm1.dtbo + +dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \ + imx8mm-cl-iot-gate-ied.dtbo \ + imx8mm-cl-iot-gate-ied-adc0.dtbo \ + imx8mm-cl-iot-gate-ied-adc1.dtbo \ + imx8mm-cl-iot-gate-ied-can0.dtbo \ + imx8mm-cl-iot-gate-ied-can1.dtbo \ + imx8mm-cl-iot-gate-ied-tpm0.dtbo \ + imx8mm-cl-iot-gate-ied-tpm1.dtbo + +ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),) +dtb-y += imx8mp-rsb3720-a1.dtb +endif + +dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb + +dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb + +dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ + corstone1000-fvp.dtb + +include $(srctree)/scripts/Makefile.dts + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += -a 0x8 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb *.dtbo *_HS diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/anx7625.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/anx7625/anx7625.c similarity index 99% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/anx7625.c rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/anx7625/anx7625.c index 0f77e3e..e584070 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/anx7625.c +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/anx7625/anx7625.c @@ -132,7 +132,7 @@ enum anx7625_pd_msg_type { #define POWER_DELIVERY_TIMEOUT 50 // [x10 = 500ms] #define OCM_LOADING_TIME 10 -#if defined(CONFIG_TARGET_PORTENTA_X8) +#if defined(CONFIG_TARGET_PORTENTA_X8) || defined(CONFIG_TARGET_IMX8MM_EVK) #define ANX7625_POWER_EN_PAD IMX_GPIO_NR(4, 25) #define ANX7625_RESET_N_PAD IMX_GPIO_NR(4, 26) #define ANX7625_CABLE_DET_PAD IMX_GPIO_NR(4, 27) diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/anx7625.h b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/anx7625/anx7625.h similarity index 100% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/anx7625.h rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/anx7625/anx7625.h diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Kconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Kconfig deleted file mode 100644 index 18abc78..0000000 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PORTENTA_X8 - -config SYS_BOARD - default "portenta-x8" - -config SYS_VENDOR - default "arduino" - -config SYS_CONFIG_NAME - default "portenta-x8" - -endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Makefile b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Makefile index 05a8273..0a66c50 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Makefile +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/Makefile @@ -4,17 +4,18 @@ # SPDX-License-Identifier: GPL-2.0+ # -#obj-y += ../../freescale/common/ -obj-y += mmc.o - -obj-y += portenta-x8.o -obj-$(CONFIG_USB_TCPC) += tcpc.o - -ifndef CONFIG_SPL_BUILD -obj-y += anx7625.o -endif +obj-y += imx8mm_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX8M_4G_LPDDR4 +obj-y += lpddr4_timing_4g.o +else obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif +endif + +ifndef CONFIG_SPL_BUILD +obj-y += anx7625.o endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/mmc.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/mmc.c deleted file mode 100644 index ab1652d..0000000 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/mmc.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include - -static int check_mmc_autodetect(void) -{ - char *autodetect_str = env_get("mmcautodetect"); - - if ((autodetect_str != NULL) && - (strcmp(autodetect_str, "yes") == 0)) { - return 1; - } - - return 0; -} - -/* This should be defined for each board */ -__weak int mmc_map_to_kernel_blk(int dev_no) -{ - return dev_no; -} - -void board_late_mmc_env_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - if (!check_mmc_autodetect()) - return; - - env_set_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", - mmc_map_to_kernel_blk(dev_no)); - env_set("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/Kconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/Kconfig deleted file mode 100644 index 5da952a..0000000 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/Kconfig +++ /dev/null @@ -1,367 +0,0 @@ -if ARCH_IMX8M - -config IMX8M - bool - select HAS_CAAM - select ROM_UNIFIED_SECTIONS - -config IMX8MQ - bool - select IMX8M - select ARMV8_SPL_EXCEPTION_VECTORS - -config IMX8MM - bool - select IMX8M - select ARMV8_SPL_EXCEPTION_VECTORS - -config IMX8MN - bool - select IMX8M - select ARMV8_SPL_EXCEPTION_VECTORS - -config IMX8MP - bool - select IMX8M - -config SYS_SOC - default "imx8m" - -config SECURE_STICKY_BITS_LOCKUP - bool "Enable workaround to fix sticky bits lock up issue" - depends on IMX8MQ && IMX_HAB - default y - -config IMX_UNIQUE_ID - hex "Enable workaround to fix sticky bits lock up issue" - depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP - default 0x0 - -config IMX8M_MCU_RDC_START_CONFIG_ADDR - hex "Start address of mcu rdc config when mcu starts" - default 0x186000 - -config IMX8M_MCU_RDC_STOP_CONFIG_ADDR - hex "Start address of mcu rdc config when mcu stops" - default 0x187000 - -choice - prompt "NXP i.MX8M board select" - optional - -config TARGET_IMX8MQ_CM - bool "Ronetix iMX8MQ-CM SoM" - select BINMAN - select IMX8MQ - select IMX8M_LPDDR4 - -config TARGET_IMX8MQ_EVK - bool "imx8mq_evk" - select IMX8MQ - select IMX8M_LPDDR4 - imply FSL_CAAM - imply FSL_BLOB - select ARCH_MISC_INIT - select SPL_CRYPTO if SPL - -config TARGET_IMX8MQ_PHANBELL - bool "imx8mq_phanbell" - select BINMAN - select IMX8MQ - select IMX8M_LPDDR4 - -config TARGET_IMX8MQ_DDR3L_VAL - bool "imx8mq_ddr3l_val" - select IMX8MQ - -config TARGET_IMX8MQ_DDR4_VAL - bool "imx8mq_ddr4_val" - select IMX8MQ - select IMX8M_DDR4 - -config TARGET_IMX8MM_DDR4_VAL - bool "imx8mm DDR4 validation board" - select IMX8MM - select SUPPORT_SPL - select IMX8M_DDR4 - -config TARGET_IMX8MM_DDR3L_VAL - bool "imx8mm DDR3L validation board" - select IMX8MM - select SUPPORT_SPL - select IMX8M_DDR3L - -config TARGET_IMX8MM_EVK - bool "imx8mm LPDDR4 EVK board" - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - imply FSL_CAAM - imply FSL_BLOB - select ARCH_MISC_INIT - select SPL_CRYPTO if SPL - -config TARGET_IMX8MM_DDR4_EVK - bool "imx8mm DDR4 EVK board" - select IMX8MM - select SUPPORT_SPL - select IMX8M_DDR4 - imply FSL_CAAM - imply FSL_BLOB - select ARCH_MISC_INIT - select SPL_CRYPTO if SPL - -config TARGET_IMX8MM_AB2 - bool "imx8mm LPDDR4 Audio board 2.0" - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - select FSL_CAAM - select FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MM_DDR4_AB2 - bool "imx8mm DDR4 Audio board 2.0" - select IMX8MM - select SUPPORT_SPL - select IMX8M_DDR4 - select FSL_CAAM - select FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MM_ICORE_MX8MM - bool "Engicam i.Core MX8M Mini SOM" - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - help - i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM. - - i.Core MX8M Mini EDIMM2.2: - * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. - * i.Core MX8M Mini needs to mount on top of EDIMM2.2 for - creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit. - - i.Core MX8M Mini C.TOUCH 2.0 - * C.TOUCH 2.0 is a general purpose Carrier board. - * i.Core MX8M Mini needs to mount on top of this Carrier board - for creating complete i.Core MX8M Mini C.TOUCH 2.0 board. - -config TARGET_IMX8MM_VENICE - bool "Support Gateworks Venice iMX8M Mini module" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_KONTRON_MX8MM - bool "Kontron Electronics N80xx" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_PORTENTA_X8 - bool "Arduino Portenta-X8" - select IMX8MM - select IMX8M_LPDDR4 - -config TARGET_IMX8MN_EVK - bool "imx8mn LPDDR4 EVK board" - select IMX8MN - select SUPPORT_SPL - select IMX8M_LPDDR4 - imply FSL_CAAM - imply FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_DDR4_EVK - bool "imx8mn DDR4 EVK board" - select IMX8MN - select SUPPORT_SPL - select IMX8M_DDR4 - imply FSL_CAAM - imply FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_DDR3_EVK - bool "imx8mn 11x11 DDR3 EVK board" - select IMX8MN - select SUPPORT_SPL - select IMX8M_DDR3L - imply FSL_CAAM - imply FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_AB2 - bool "imx8mn LPDDR4 Audio board 2.0" - select IMX8MN - select SUPPORT_SPL - select IMX8M_LPDDR4 - select FSL_CAAM - select FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_DDR4_AB2 - bool "imx8mn DDR4 Audio board 2.0" - select IMX8MN - select SUPPORT_SPL - select IMX8M_DDR4 - select FSL_CAAM - select FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_DDR3L_AB2 - bool "imx8mn DDR3L Audio board 2.0" - select IMX8MN - select SUPPORT_SPL - select IMX8M_DDR3L - select FSL_CAAM - select FSL_BLOB - select SPL_CRYPTO if SPL - -config TARGET_IMX8MN_VENICE - bool "Support Gateworks Venice iMX8M Nano module" - select BINMAN - select IMX8MN - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_IMX8MP_EVK - bool "imx8mp LPDDR4 EVK board" - select IMX8MP - select SUPPORT_SPL - select IMX8M_LPDDR4 - imply FSL_CAAM - imply FSL_BLOB - select ARCH_MISC_INIT - select SPL_CRYPTO if SPL - -config TARGET_IMX8MP_DDR4_EVK - bool "imx8mp DDR4 EVK board" - select IMX8MP - select SUPPORT_SPL - select IMX8M_DDR4 - imply FSL_CAAM - imply FSL_BLOB - select ARCH_MISC_INIT - select SPL_CRYPTO if SPL - -config TARGET_PICO_IMX8MQ - bool "Support Technexion Pico iMX8MQ" - select BINMAN - select IMX8MQ - select IMX8M_LPDDR4 - -config TARGET_IMX8MN_VAR_SOM - bool "imx8mn_var_som" - select BINMAN - select IMX8MN - select SUPPORT_SPL - select IMX8M_DDR4 - -config TARGET_KONTRON_PITX_IMX8M - bool "Support Kontron pITX-imx8m" - select BINMAN - select IMX8MQ - select IMX8M_LPDDR4 - -config TARGET_VERDIN_IMX8MM - bool "Support Toradex Verdin iMX8M Mini module" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_VERDIN_IMX8MP - bool "Support Toradex Verdin iMX8M Plus module" - select BINMAN - select IMX8MP - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_IMX8MM_BEACON - bool "imx8mm Beacon Embedded devkit" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_IMX8MN_BEACON - bool "imx8mn Beacon Embedded devkit" - select BINMAN - select IMX8MN - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_PHYCORE_IMX8MM - bool "PHYTEC PHYCORE i.MX8MM" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_PHYCORE_IMX8MP - bool "PHYTEC PHYCORE i.MX8MP" - select BINMAN - select IMX8MP - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_IMX8MM_CL_IOT_GATE - bool "CompuLab iot-gate-imx8" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - select SUPPORT_EXTENSION_SCAN - -config TARGET_IMX8MM_CL_IOT_GATE_OPTEE - bool "CompuLab iot-gate-imx8 with optee support" - select BINMAN - select IMX8MM - select SUPPORT_SPL - select IMX8M_LPDDR4 - select SUPPORT_EXTENSION_SCAN - -config TARGET_IMX8MP_RSB3720A1_4G - bool "Support i.MX8MP RSB3720A1 4G" - select BINMAN - select IMX8MP - select SUPPORT_SPL - select IMX8M_LPDDR4 - -config TARGET_IMX8MP_RSB3720A1_6G - bool "Support i.MX8MP RSB3720A1 6G" - select BINMAN - select IMX8MP - select SUPPORT_SPL - select IMX8M_LPDDR4 -endchoice - -source "board/advantech/imx8mp_rsb3720a1/Kconfig" -source "board/beacon/imx8mm/Kconfig" -source "board/beacon/imx8mn/Kconfig" -source "board/compulab/imx8mm-cl-iot-gate/Kconfig" -source "board/engicam/imx8mm/Kconfig" -source "board/arduino/portenta-x8/Kconfig" -source "board/freescale/imx8mq_evk/Kconfig" -source "board/freescale/imx8mq_val/Kconfig" -source "board/freescale/imx8mm_ab2/Kconfig" -source "board/freescale/imx8mm_evk/Kconfig" -source "board/freescale/imx8mm_val/Kconfig" -source "board/freescale/imx8mn_evk/Kconfig" -source "board/freescale/imx8mp_evk/Kconfig" -source "board/gateworks/venice/Kconfig" -source "board/google/imx8mq_phanbell/Kconfig" -source "board/kontron/pitx_imx8m/Kconfig" -source "board/kontron/sl-mx8mm/Kconfig" -source "board/phytec/phycore_imx8mm/Kconfig" -source "board/phytec/phycore_imx8mp/Kconfig" -source "board/ronetix/imx8mq-cm/Kconfig" -source "board/technexion/pico-imx8mq/Kconfig" -source "board/variscite/imx8mn_var_som/Kconfig" -source "board/toradex/verdin-imx8mm/Kconfig" -source "board/toradex/verdin-imx8mp/Kconfig" - -endif diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/fat.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/fat.c deleted file mode 100644 index 818bbff..0000000 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/fat.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (c) Copyright 2011 by Tigris Elektronik GmbH - * - * Author: - * Maximilian Schwerin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SPL_BUILD -/* TODO(sjg@chromium.org): Figure out why this is needed */ -# if !defined(CONFIG_TARGET_AM335X_EVM) || defined(CONFIG_SPL_OS_BOOT) -# define LOADENV -# endif -#else -# define LOADENV -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static char *env_fat_device_and_part(void) -{ -#ifdef CONFIG_MMC - static char *part_str; - - if (!part_str) { - part_str = CONFIG_ENV_FAT_DEVICE_AND_PART; - sprintf(part_str, "%d:1", mmc_get_env_dev()); - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') { - part_str = "0" CONFIG_ENV_FAT_DEVICE_AND_PART; - part_str[0] += mmc_get_env_dev(); - } - } - - return part_str; -#else - return CONFIG_ENV_FAT_DEVICE_AND_PART; -#endif -} - -static int env_fat_save(void) -{ - env_t __aligned(ARCH_DMA_MINALIGN) env_new; - struct blk_desc *dev_desc = NULL; - struct disk_partition info; - const char *file = CONFIG_ENV_FAT_FILE; - int dev, part; - int err; - loff_t size; - - err = env_export(&env_new); - if (err) - return err; - - part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, - env_fat_device_and_part(), - &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->devnum; - if (fat_set_blk_dev(dev_desc, &info) != 0) { - /* - * This printf is embedded in the messages from env_save that - * will calling it. The missing \n is intentional. - */ - printf("Unable to use %s %d:%d... \n", - CONFIG_ENV_FAT_INTERFACE, dev, part); - return 1; - } - -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - if (gd->env_valid == ENV_VALID) - file = CONFIG_ENV_FAT_FILE_REDUND; -#endif - - err = file_fat_write(file, (void *)&env_new, 0, sizeof(env_t), &size); - if (err == -1) { - /* - * This printf is embedded in the messages from env_save that - * will calling it. The missing \n is intentional. - */ - printf("Unable to write \"%s\" from %s%d:%d... \n", - file, CONFIG_ENV_FAT_INTERFACE, dev, part); - return 1; - } - -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - gd->env_valid = (gd->env_valid == ENV_REDUND) ? ENV_VALID : ENV_REDUND; -#endif - - return 0; -} - -#ifdef LOADENV -static int env_fat_load(void) -{ - ALLOC_CACHE_ALIGN_BUFFER(char, buf1, CONFIG_ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - ALLOC_CACHE_ALIGN_BUFFER(char, buf2, CONFIG_ENV_SIZE); - int err2; -#endif - struct blk_desc *dev_desc = NULL; - struct disk_partition info; - int dev, part; - int err1; - -#ifdef CONFIG_MMC - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc")) - mmc_initialize(NULL); -#endif - - part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, - env_fat_device_and_part(), - &dev_desc, &info, 1); - if (part < 0) - goto err_env_relocate; - - dev = dev_desc->devnum; - if (fat_set_blk_dev(dev_desc, &info) != 0) { - /* - * This printf is embedded in the messages from env_save that - * will calling it. The missing \n is intentional. - */ - printf("Unable to use %s %d:%d... \n", - CONFIG_ENV_FAT_INTERFACE, dev, part); - goto err_env_relocate; - } - - err1 = file_fat_read(CONFIG_ENV_FAT_FILE, buf1, CONFIG_ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - err2 = file_fat_read(CONFIG_ENV_FAT_FILE_REDUND, buf2, CONFIG_ENV_SIZE); - - err1 = (err1 >= 0) ? 0 : -1; - err2 = (err2 >= 0) ? 0 : -1; - return env_import_redund(buf1, err1, buf2, err2, H_EXTERNAL); -#else - if (err1 < 0) { - /* - * This printf is embedded in the messages from env_save that - * will calling it. The missing \n is intentional. - */ - printf("Unable to read \"%s\" from %s%d:%d... \n", - CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part); - goto err_env_relocate; - } - - return env_import(buf1, 1, H_EXTERNAL); -#endif - -err_env_relocate: - env_set_default(NULL, 0); - - return -EIO; -} -#endif /* LOADENV */ - -U_BOOT_ENV_LOCATION(fat) = { - .location = ENVL_FAT, - ENV_NAME("FAT") -#ifdef LOADENV - .load = env_fat_load, -#endif - .save = ENV_SAVE_PTR(env_fat_save), -}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/spl_mmc.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/spl_mmc.c deleted file mode 100644 index c327198..0000000 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/common/spl_mmc.c +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Texas Instruments, - * - * Aneesh V - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int mmc_load_legacy(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, - ulong sector, struct legacy_img_hdr *header) -{ - u32 image_offset_sectors; - u32 image_size_sectors; - unsigned long count; - u32 image_offset; - int ret; - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) - return ret; - - /* convert offset to sectors - round down */ - image_offset_sectors = spl_image->offset / mmc->read_bl_len; - /* calculate remaining offset */ - image_offset = spl_image->offset % mmc->read_bl_len; - - /* convert size to sectors - round up */ - image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) / - mmc->read_bl_len; - - /* Read the header too to avoid extra memcpy */ - count = blk_dread(mmc_get_blk_desc(mmc), - sector + image_offset_sectors, - image_size_sectors, - (void *)(ulong)spl_image->load_addr); - debug("read %x sectors to %lx\n", image_size_sectors, - spl_image->load_addr); - if (count != image_size_sectors) - return -EIO; - - if (image_offset) - memmove((void *)(ulong)spl_image->load_addr, - (void *)(ulong)spl_image->load_addr + image_offset, - spl_image->size); - - return 0; -} - -ulong __weak h_spl_load_read(struct spl_load_info *load, ulong sector, - ulong count, void *buf) -{ - struct mmc *mmc = load->dev; - - return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); -} - -static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part) -{ -#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR) - if (part == 0) - return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET; -#endif - - return 0; -} - -#if defined(CONFIG_DUAL_BOOTLOADER) -int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image, - struct mmc *mmc); -#endif - -int __weak mmc_image_load_late(struct spl_image_info *spl_image, struct mmc *mmc) -{ - return 0; -} - -static __maybe_unused -int mmc_load_image_raw_sector(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, unsigned long sector) -{ - unsigned long count; - struct legacy_img_hdr *header; - struct blk_desc *bd = mmc_get_blk_desc(mmc); - int ret = 0; - - header = spl_get_load_buffer(-sizeof(*header), bd->blksz); - - /* read image header to find the image size & load address */ - count = blk_dread(bd, sector, 1, header); - debug("hdr read sector %lx, count=%lu\n", sector, count); - if (count == 0) { - ret = -EIO; - goto end; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.dev = mmc; - load.priv = NULL; - load.filename = NULL; - load.bl_len = mmc->read_bl_len; - load.read = h_spl_load_read; - ret = spl_load_simple_fit(spl_image, &load, sector, header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { - struct spl_load_info load; - - load.dev = mmc; - load.priv = NULL; - load.filename = NULL; - load.bl_len = mmc->read_bl_len; - load.read = h_spl_load_read; - - ret = spl_load_imx_container(spl_image, &load, sector); - } else { - ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header); - } - -end: - if (ret) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("mmc_load_image_raw_sector: mmc block read error\n"); -#endif - return -1; - } - - ret = mmc_image_load_late(spl_image, mmc); - return ret; -} - -static int spl_mmc_get_device_index(u32 boot_device) -{ - switch (boot_device) { - case BOOT_DEVICE_MMC1: - return 0; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - return 1; - } - -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: unsupported mmc boot device.\n"); -#endif - - return -ENODEV; -} - -static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) -{ - int err, mmc_dev; - - mmc_dev = spl_mmc_get_device_index(boot_device); - if (mmc_dev < 0) - return mmc_dev; - -#if CONFIG_IS_ENABLED(DM_MMC) - err = mmc_init_device(mmc_dev); -#else - err = mmc_initialize(NULL); -#endif /* DM_MMC */ - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not initialize mmc. error: %d\n", err); -#endif - return err; - } - *mmcp = find_mmc_device(mmc_dev); - err = *mmcp ? 0 : -ENODEV; - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: could not find mmc device %d. error: %d\n", - mmc_dev, err); -#endif - return err; - } - - return 0; -} - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION -static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, int partition, - unsigned long sector) -{ - struct disk_partition info; - int err; - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE - int type_part; - /* Only support MBR so DOS_ENTRY_NUMBERS */ - for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) { - err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); - if (err) - continue; - if (info.sys_ind == - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { - partition = type_part; - break; - } - } -#endif - - err = part_get_info(mmc_get_blk_desc(mmc), partition, &info); - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: partition error\n"); -#endif - return -1; - } - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR - return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start + sector); -#else - return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start); -#endif -} -#endif - -#if CONFIG_IS_ENABLED(FALCON_BOOT_MMCSD) -static int mmc_load_image_raw_os(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc) -{ - int ret; - -#if CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR) - unsigned long count; - - count = blk_dread(mmc_get_blk_desc(mmc), - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, - CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS, - (void *) CONFIG_SYS_SPL_ARGS_ADDR); - if (count != CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("mmc_load_image_raw_os: mmc block read error\n"); -#endif - return -1; - } -#endif /* CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR */ - - ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc, - CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); - if (ret) - return ret; - - if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) { - puts("Expected image is not found. Trying to start U-boot\n"); - return -ENOENT; - } - - return 0; -} -#else -static int mmc_load_image_raw_os(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc) -{ - return -ENOSYS; -} -#endif - -#ifndef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - return 1; -} -#endif - -#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION -static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, - const char *filename) -{ - int err = -ENOSYS; - - __maybe_unused int partition = CONFIG_SYS_MMCSD_FS_BOOT_PARTITION; - -#if CONFIG_SYS_MMCSD_FS_BOOT_PARTITION == -1 - { - struct disk_partition info; - debug("Checking for the first MBR bootable partition\n"); - for (int type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) { - err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); - if (err) - continue; - debug("Partition %d is of type %d and bootable=%d\n", type_part, info.sys_ind, info.bootable); - if (info.bootable != 0) { - debug("Partition %d is bootable, using it\n", type_part); - partition = type_part; - break; - } - } - printf("Using first bootable partition: %d\n", partition); - if (partition == CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) { - return -ENOSYS; - } - } -#endif - -#ifdef CONFIG_SPL_FS_FAT - if (!spl_start_uboot()) { - err = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition); - if (!err) - return err; - } -#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition, - filename); - if (!err) - return err; -#endif -#endif -#ifdef CONFIG_SPL_FS_EXT4 - if (!spl_start_uboot()) { - err = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition); - if (!err) - return err; - } -#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc), - partition, - filename); - if (!err) - return err; -#endif -#endif - -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - err = -ENOENT; -#endif - - return err; -} -#else -static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, - const char *filename) -{ - return -ENOSYS; -} -#endif - -u32 __weak spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#elif defined(CONFIG_SUPPORT_EMMC_BOOT) - return MMCSD_MODE_EMMCBOOT; -#else - return MMCSD_MODE_RAW; -#endif -} - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION -int __weak spl_mmc_boot_partition(const u32 boot_device) -{ - return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION; -} -#endif - -unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc, - unsigned long raw_sect) -{ - return raw_sect; -} - -int default_spl_mmc_emmc_boot_partition(struct mmc *mmc) -{ - int part; -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION - part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION; -#else - /* - * We need to check what the partition is configured to. - * 1 and 2 match up to boot0 / boot1 and 7 is user data - * which is the first physical partition (0). - */ -#ifdef CONFIG_DUAL_BOOTLOADER - /* Bootloader is stored in eMMC user partition for - * dual bootloader. - */ - part = 0; -#else - part = (mmc->part_config >> 3) & PART_ACCESS_MASK; - if (part == 7) - part = 0; -#endif -#endif - - return part; -} - -int __weak spl_mmc_emmc_boot_partition(struct mmc *mmc) -{ - return default_spl_mmc_emmc_boot_partition(mmc); -} - -static int spl_mmc_get_mmc_devnum(struct mmc *mmc) -{ - struct blk_desc *block_dev; -#if !CONFIG_IS_ENABLED(BLK) - block_dev = &mmc->block_dev; -#else - block_dev = dev_get_uclass_plat(mmc->dev); -#endif - return block_dev->devnum; -} - -int spl_mmc_load(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - const char *filename, - int raw_part, - unsigned long raw_sect) -{ - static struct mmc *mmc; - u32 boot_mode; - int err = 0; - __maybe_unused int part = 0; - int mmc_dev; - - /* Perform peripheral init only once for an mmc device */ - mmc_dev = spl_mmc_get_device_index(bootdev->boot_device); - if (!mmc || spl_mmc_get_mmc_devnum(mmc) != mmc_dev) { - err = spl_mmc_find_device(&mmc, bootdev->boot_device); - if (err) - return err; - - err = mmc_init(mmc); - if (err) { - mmc = NULL; -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("spl: mmc init failed with error: %d\n", err); -#endif - return err; - } - } - - boot_mode = spl_mmc_boot_mode(mmc, bootdev->boot_device); - err = -EINVAL; - - /* Using fall through from MMCSD_MODE_EMMCBOOT to MMCSD_MODE_FS. - This allows to use both modes. */ - boot_mode = MMCSD_MODE_EMMCBOOT; - - switch (boot_mode) { - case MMCSD_MODE_EMMCBOOT: - part = spl_mmc_emmc_boot_partition(mmc); - - if (CONFIG_IS_ENABLED(MMC_TINY)) - err = mmc_switch_part(mmc, part); - else - err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); - - if (err) { -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - puts("spl: mmc partition switch failed\n"); -#endif - return err; - } - /* Fall through */ - case MMCSD_MODE_RAW: - debug("spl: mmc boot mode: raw\n"); - - if (!spl_start_uboot()) { - err = mmc_load_image_raw_os(spl_image, bootdev, mmc); - if (!err) - return err; - } - -#ifndef CONFIG_DUAL_BOOTLOADER - raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect); -#endif - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - err = mmc_load_image_raw_partition(spl_image, bootdev, - mmc, raw_part, - raw_sect); - if (!err) - return err; -#endif -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#ifdef CONFIG_DUAL_BOOTLOADER - err = mmc_load_image_raw_sector_dual_uboot(spl_image, mmc); -#else - err = mmc_load_image_raw_sector(spl_image, bootdev, mmc, - raw_sect + spl_mmc_raw_uboot_offset(part)); -#endif - if (!err) - return err; -#endif - /* If RAW mode fails, try FS mode. */ - case MMCSD_MODE_FS: - debug("spl: mmc boot mode: fs\n"); - - err = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename); - if (!err) - return err; - - break; -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - default: - puts("spl: mmc: wrong boot mode\n"); -#endif - } - - return err; -} - -int spl_mmc_load_image(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev) -{ - return spl_mmc_load(spl_image, bootdev, -#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, -#else - NULL, -#endif -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION - spl_mmc_boot_partition(bootdev->boot_device), -#else - 0, -#endif -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR -#ifdef CONFIG_SECONDARY_BOOT_SECTOR_OFFSET - + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET -#endif - ); -#else - 0); -#endif -} - -SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image); -SPL_LOAD_IMAGE_METHOD("MMC2", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image); -SPL_LOAD_IMAGE_METHOD("MMC2_2", 0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image); diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8-u-boot.dtsi b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk-u-boot.dtsi similarity index 52% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8-u-boot.dtsi rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk-u-boot.dtsi index 9a2de71..e417df4 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8-u-boot.dtsi +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk-u-boot.dtsi @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ +#include "imx8mm-u-boot.dtsi" + / { wdt-reboot { compatible = "wdt-reboot"; @@ -37,134 +39,157 @@ }; }; -&{/soc@0} { - u-boot,dm-pre-reloc; +&aips4 { u-boot,dm-spl; }; -&A53_0 { - /delete-property/ cpu-idle-states; +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; }; -&A53_1 { - /delete-property/ cpu-idle-states; +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; }; -&A53_2 { - /delete-property/ cpu-idle-states; +&pinctrl_uart3 { + u-boot,dm-spl; }; -&A53_3 { - /delete-property/ cpu-idle-states; +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; }; -&clk { +&pinctrl_usdhc2 { u-boot,dm-spl; - u-boot,dm-pre-reloc; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; }; -&osc_24m { +&pinctrl_usdhc3 { u-boot,dm-spl; - u-boot,dm-pre-reloc; }; -&aips1 { +&gpio1 { u-boot,dm-spl; - u-boot,dm-pre-reloc; }; -&aips3 { +&gpio2 { u-boot,dm-spl; }; -&iomuxc { +&gpio3 { u-boot,dm-spl; }; -&usdhc2 { +&gpio4 { u-boot,dm-spl; - sd-uhs-sdr104; - sd-uhs-ddr50; - fsl,signal-voltage-switch-extra-delay-ms = <8>; }; -&usdhc3 { +&gpio5 { u-boot,dm-spl; - mmc-hs400-1_8v; }; -&i2c1 { +&uart3 { u-boot,dm-spl; }; -&i2c2 { +&crypto { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { +&sec_jr0 { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} { +&sec_jr1 { u-boot,dm-spl; }; -&pinctrl_i2c1 { +&sec_jr2 { u-boot,dm-spl; }; -&pinctrl_i2c2 { +&usbmisc1 { u-boot,dm-spl; }; -&pinctrl_pmic { +&usbphynop1 { u-boot,dm-spl; }; -&gpio1 { +&usbotg1 { u-boot,dm-spl; }; -&gpio2 { +&usdhc1 { u-boot,dm-spl; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; }; -&gpio3 { +&usdhc2 { u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + fsl,signal-voltage-switch-extra-delay-ms = <8>; }; -&gpio4 { +&usdhc3 { u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; }; -&gpio5 { +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/bd71847@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/bd71847@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_wdog { u-boot,dm-spl; }; &fec1 { phy-reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - phy-reset-post-delay = <1>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; }; -&wdog1 { - u-boot,dm-spl; +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; -&flexspi { - assigned-clock-rates = <100000000>; - assigned-clocks = <&clk IMX8MM_CLK_QSPI>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; +&wdog1 { + u-boot,dm-spl; }; -&lcdif { - enable_polarity_low; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ assigned-clock-rates; +&usbotg1 { + status = "okay"; }; &mipi_dsi { diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dts b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dts new file mode 100644 index 0000000..7ed4c9d --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm-evk.dtsi" + +/ { + model = "Arduino Portenta X8 i.MX8MM board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; + }; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; +}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8.dts b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dtsi similarity index 57% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8.dts rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dtsi index 7652138..5928e12 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/devicetree/portenta-x8.dts +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-evk.dtsi @@ -1,27 +1,16 @@ -/** - * Copyright 2020 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020,2022 NXP */ /dts-v1/; +#include +#include #include "imx8mm.dtsi" / { - model = "Arduino Portenta X8 i.MX8MM board"; - compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; - chosen { - bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; stdout-path = &uart3; }; @@ -66,13 +55,6 @@ off-on-delay-us = <20000>; enable-active-high; }; - - /* Y2 SIT1532AI */ - pmic_refclk: pmic-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; }; &A53_0 { @@ -91,26 +73,7 @@ cpu-supply = <&buck2_reg>; }; -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - +/* Connected to ext. STM32H7, no driver in spl/u-boot, see X8H7 in kernel */ &ecspi3 { #address-cells = <1>; #size-cells = <0>; @@ -119,6 +82,12 @@ num-cs = <1>; cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; }; &fec1 { @@ -135,11 +104,17 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&gpio3>; - interrupts = <7 0>; + reg = <0>; reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + qca,disable-smarteee; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; @@ -163,12 +138,13 @@ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; - pmic@4b { + pmic_nxp: bd71847@4b { compatible = "rohm,bd71847"; reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; interrupt-parent = <&gpio3>; - interrupts = <8 GPIO_ACTIVE_LOW>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -192,8 +168,8 @@ rohm,dvs-idle-voltage = <900000>; }; + /* BUCK5 in Datasheet */ buck3_reg: BUCK3 { - // BUCK5 in datasheet regulator-name = "BUCK3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; @@ -201,8 +177,8 @@ regulator-always-on; }; + /* BUCK6 in Datasheet */ buck4_reg: BUCK4 { - // BUCK6 in datasheet regulator-name = "BUCK4"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -210,8 +186,8 @@ regulator-always-on; }; + /* BUCK7 in Datasheet */ buck5_reg: BUCK5 { - // BUCK7 in datasheet regulator-name = "BUCK5"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; @@ -219,8 +195,8 @@ regulator-always-on; }; + /* BUCK8 in Datasheet */ buck6_reg: BUCK6 { - // BUCK8 in datasheet regulator-name = "BUCK6"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; @@ -260,6 +236,15 @@ regulator-always-on; }; + /* @TODO: supplies anx7625, handled in spl.c */ + /*ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + };*/ + ldo6_reg: LDO6 { regulator-name = "LDO6"; regulator-min-microvolt = <900000>; @@ -281,12 +266,17 @@ status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +/* SoM USBC Port Connector J3 */ &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -297,6 +287,13 @@ samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; + + /* @TODO: connector should go to anx7625 */ + /*port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + };*/ }; &usbotg2 { @@ -320,19 +317,6 @@ status = "okay"; }; -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - /* TODO: lowered speed here from 400000000 */ - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -346,24 +330,16 @@ pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 >; }; - pinctrl_ecspi3_cs: ecspi3cs { + pinctrl_ecspi3_cs: ecspi3csgrp { fsl,pins = < - // MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x40000 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 + /* MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x40000*/ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000 >; }; @@ -383,8 +359,16 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x16 - MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x41 + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x16 /* ENET_nRST */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x41 /* ENET_nINT */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 >; }; @@ -393,7 +377,7 @@ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; - }; + }; pinctrl_i2c2: i2c2grp { fsl,pins = < @@ -409,143 +393,96 @@ >; }; - pinctrl_i2c1_gpio: i2c1grp-gpio { + pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 >; }; - pinctrl_i2c2_gpio: i2c2grp-gpio { + pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 >; }; - pinctrl_i2c3_gpio: i2c3grp-gpio { + pinctrl_i2c3_gpio: i2c3-gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x141 >; }; - pinctrl_uart3: uart3grp { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; /* Some of these pins are leaved configured by internal ROM code */ + /* NOTE: ext. STM32H7 pins, see also ecspi3 */ pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x110 /* NRST_STM32 Pull Down */ @@ -557,15 +494,15 @@ >; }; - /* Anx7625 pins */ + /* @TODO: anx7625 pins, need proper u-boot driver impl. */ pinctrl_hog_2: hoggrp-2 { fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* POWER_EN */ - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x51 /* CABLE_DET */ - MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x151 /* ALERT_N */ - MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 /* RESET_N */ - MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* VBUS_CTL */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* EN_I2S */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* POWER_EN */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x51 /* CABLE_DET */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x151 /* ALERT_N */ + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 /* RESET_N */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* VBUS_CTL */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* EN_I2S */ >; }; }; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-u-boot.dtsi b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-u-boot.dtsi new file mode 100644 index 0000000..277d82e --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm-u-boot.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Jagan Teki + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&soc { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + + blob_1d_imem: ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + blob_1d_dmem: ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + blob_2d_imem: ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + + blob_2d_dmem: ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + fit,external-offset = ; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = ; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + +#ifndef CONFIG_ARMV8_PSCI + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x920000>; + load = <0x920000>; + type = "firmware"; + + atf-blob { + filename = "bl31.bin"; + type = "atf-bl31"; + }; + }; +#endif + + binman_fip: fip { + arch = "arm64"; + compression = "none"; + description = "Trusted Firmware FIP"; + load = <0x40310000>; + type = "firmware"; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + binman_configuration: @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; +#ifndef CONFIG_ARMV8_PSCI + loadables = "atf"; +#endif + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + +#ifdef CONFIG_FSPI_CONF_HEADER + fspi_conf_block { + filename = CONFIG_FSPI_CONF_FILE; + type = "blob-ext"; + size = <0x1000>; + }; + + spl { + filename = "spl.bin"; + offset = <0x1000>; + type = "blob-ext"; + }; + + binman_uboot: uboot { + filename = "u-boot.itb"; + offset = <0x58C00>; + type = "blob-ext"; + }; +#else + spl { + filename = "spl.bin"; + offset = <0x0>; + type = "blob-ext"; + }; + + binman_uboot: uboot { + filename = "u-boot.itb"; + offset = <0x57c00>; + type = "blob-ext"; + }; +#endif + }; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&spba1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&spba2 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.c similarity index 96% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.c rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.c index e9440d5..4cbb1d5 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.c +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018 NXP */ #include #include @@ -18,7 +18,7 @@ #include #include #include -#include "../../freescale/common/tcpc.h" +#include "../common/tcpc.h" #include #include @@ -336,7 +336,7 @@ int board_phy_config(struct phy_device *phydev) } #endif -#if defined(CONFIG_USB_TCPC) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_USB_TCPC struct tcpc_port port1; struct tcpc_port port2; @@ -521,9 +521,6 @@ int board_usb_cleanup(int index, enum usb_init_type init) } #endif -#define DISPMIX 9 -#define MIPI 10 - #define FEC_RST_PAD IMX_GPIO_NR(3, 6) static void setup_iomux_fec(void) @@ -543,11 +540,9 @@ static void setup_iomux_fec(void) int board_init(void) { - struct arm_smccc_res res; - model = &carrier_unknown; -#if defined(CONFIG_USB_TCPC) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_USB_TCPC setup_typec(); #endif @@ -562,11 +557,6 @@ int board_init(void) anx7625_probe(1); #endif - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - DISPMIX, true, 0, 0, 0, 0, &res); - arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, - MIPI, true, 0, 0, 0, 0, &res); - #ifdef EXT_USB_HUB ext_usb_hub_init(); #endif @@ -639,7 +629,7 @@ bool is_power_key_pressed(void) { #ifdef CONFIG_ANDROID_RECOVERY int is_recovery_key_pressing(void) { - return 0; /*TODO*/ + return 0; /* TODO */ } -#endif /*CONFIG_ANDROID_RECOVERY*/ -#endif /*CONFIG_FSL_FASTBOOT*/ +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.h b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.h similarity index 97% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.h rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.h index dc0a2d2..9359b5d 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8.h +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk.h @@ -3,8 +3,8 @@ * Copyright 2019 NXP */ -#ifndef __PORTENTA_M8_H -#define __PORTENTA_M8_H +#ifndef __IMX8MM_EVK_H +#define __IMX8MM_EVK_H #include #include @@ -51,7 +51,7 @@ * Another approach is add the clocks for inmates into clks_init_on * in clk-imx8mm.c, then clk_ingore_unused could be removed. */ -#define JH_ROOT_DTB "portenta-x8.dtb" +#define JH_ROOT_DTB "imx8mm-evk-root.dtb" #define JAILHOUSE_ENV \ "jh_clk= \0 " \ @@ -180,7 +180,11 @@ #define CFG_MXC_UART_BASE UART_BASE_ADDR(3) +#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK +#define CFG_SYS_FSL_USDHC_NUM 1 +#else #define CFG_SYS_FSL_USDHC_NUM 2 +#endif #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_NAND_BASE 0x20000000 diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8_defconfig b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk_defconfig similarity index 97% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8_defconfig rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk_defconfig index 0bca4f8..c16e756 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/portenta-x8_defconfig +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/imx8mm_evk_defconfig @@ -14,14 +14,14 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x7E1000 -CONFIG_TARGET_PORTENTA_X8=y +CONFIG_TARGET_IMX8MM_EVK=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x920000 CONFIG_SPL=y -CONFIG_DEFAULT_DEVICE_TREE="portenta-x8" +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" CONFIG_CSF_SIZE=0x2000 CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_LTO=y @@ -56,7 +56,7 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_NR_DRAM_BANKS=2 # CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_IMPORTENV=y CONFIG_CMD_CRC32=y CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set @@ -94,7 +94,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_DEFAULT_FDT_FILE="portenta-x8.dtb" +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 @@ -154,6 +154,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/lpddr4_timing.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/lpddr4_timing.c similarity index 100% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/lpddr4_timing.c rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/lpddr4_timing.c diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/spl.c b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/spl.c similarity index 94% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/spl.c rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/spl.c index 22f8909..1c8bd58 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/board/spl.c +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x8/spl.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP - * + * Copyright 2019, 2021 NXP */ #include @@ -229,29 +228,6 @@ int power_init_board(void) return 0; } #else -#define POWER_BD71837_I2C_BUS 1 -#define POWER_BD71837_I2C_ADDR 0x4B - -int power_bd71837_init(unsigned char bus) -{ - static const char name[] = BD718XX_REGULATOR_DRIVER; - struct pmic *p = pmic_alloc(); - - if (!p) { - log_err("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - p->name = name; - p->interface = I2C_PMIC; - p->number_of_regs = BD718XX_MAX_REGISTER; - p->hw.i2c.addr = POWER_BD71837_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - return 0; -} - int power_init_board(void) { struct pmic *p; diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x9/portenta-x9.h b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x9/portenta-x9.h index 418455a..f766c46 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x9/portenta-x9.h +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx/portenta-x9/portenta-x9.h @@ -78,7 +78,7 @@ "boot_fit=no\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0x10000000\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx_%.bbappend b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx_%.bbappend index 916ccab..da63ef4 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx_%.bbappend +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-imx_%.bbappend @@ -1,24 +1,51 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" SRC_URI:append:portenta-x8 = " \ - file://board/anx7625.c \ - file://board/anx7625.h \ - file://board/Kconfig \ - file://board/lpddr4_timing.c \ + file://Makefile \ file://board/Makefile \ - file://board/mmc.c \ - file://board/portenta-x8.c \ - file://board/portenta-x8_defconfig \ - file://board/portenta-x8.h \ - file://board/spl.c \ - file://devicetree/Makefile \ - file://devicetree/portenta-x8.dts \ - file://devicetree/portenta-x8-u-boot.dtsi \ - file://common/fat.c \ - file://common/Kconfig \ - file://common/spl_mmc.c \ + file://imx8mm_evk_defconfig \ + file://imx8mm-evk.dts \ + file://imx8mm-evk.dtsi \ + file://imx8mm-evk-u-boot.dtsi \ + file://imx8mm-u-boot.dtsi \ + file://imx8mm_evk.h \ + file://imx8mm_evk.c \ + file://spl.c \ + file://lpddr4_timing.c \ + file://anx7625/anx7625.c \ + file://anx7625/anx7625.h \ " +do_override_files_portenta_x8 () { + bbwarn Overriding files for ${MACHINE} + + # Override Makefile + cp ${WORKDIR}/Makefile ${S}/arch/arm/dts/Makefile + + # Override Board Makefile + cp ${WORKDIR}/board/Makefile ${S}/board/freescale/imx8mm_evk/Makefile + + # @TODO: inspect UBOOT_CONFIG_BASENAME for defconfig in use + cp ${WORKDIR}/imx8mm_evk_defconfig ${S}/configs/imx8mm_evk_defconfig + + cp ${WORKDIR}/imx8mm-evk.dts ${S}/arch/arm/dts/imx8mm-evk.dts + cp ${WORKDIR}/imx8mm-evk.dtsi ${S}/arch/arm/dts/imx8mm-evk.dtsi + + # @TODO: u-boot auto-includes the *-u-boot.dtsi prepending MACHINE to the board devicetree + # see scripts/Makefile.lib, so should never be included directly from board devicetree + cp ${WORKDIR}/imx8mm-evk-u-boot.dtsi ${S}/arch/arm/dts/imx8mm-evk-u-boot.dtsi + cp ${WORKDIR}/imx8mm-u-boot.dtsi ${S}/arch/arm/dts/imx8mm-u-boot.dtsi + + cp ${WORKDIR}/imx8mm_evk.c ${S}/board/freescale/imx8mm_evk/imx8mm_evk.c + cp ${WORKDIR}/lpddr4_timing.c ${S}/board/freescale/imx8mm_evk/lpddr4_timing.c + cp ${WORKDIR}/spl.c ${S}/board/freescale/imx8mm_evk/spl.c + + cp ${WORKDIR}/imx8mm_evk.h ${S}/include/configs/imx8mm_evk.h + + cp ${WORKDIR}/anx7625/anx7625.c ${S}/board/freescale/imx8mm_evk/anx7625.c + cp ${WORKDIR}/anx7625/anx7625.h ${S}/board/freescale/imx8mm_evk/anx7625.h +} + SRC_URI:append:portenta-x9 = " \ file://Makefile \ file://portenta-x9_defconfig \ @@ -31,35 +58,13 @@ SRC_URI:append:portenta-x9 = " \ file://portenta-x9.h \ " -do_override_files_portenta_x8 () { - # Overrides - cp ${WORKDIR}/common/Kconfig ${S}/arch/arm/mach-imx/imx8m/Kconfig - cp ${WORKDIR}/common/fat.c ${S}/env/fat.c - #cp ${WORKDIR}/common/spl_mmc.c ${S}/common/spl/spl_mmc.c - cp ${WORKDIR}/devicetree/Makefile ${S}/arch/arm/dts/Makefile - - # Machine files (new) - cp ${WORKDIR}/devicetree/portenta-x8.dts ${S}/arch/arm/dts/portenta-x8.dts - cp ${WORKDIR}/devicetree/portenta-x8-u-boot.dtsi ${S}/arch/arm/dts/portenta-x8-u-boot.dtsi - cp ${WORKDIR}/board/portenta-x8_defconfig ${S}/configs/portenta-x8_defconfig - cp ${WORKDIR}/board/portenta-x8.h ${S}/include/configs/portenta-x8.h - - mkdir -p ${S}/board/arduino/portenta-x8 - cp ${WORKDIR}/board/Makefile ${S}/board/arduino/portenta-x8/Makefile - cp ${WORKDIR}/board/Kconfig ${S}/board/arduino/portenta-x8/Kconfig - cp ${WORKDIR}/board/anx7625.h ${S}/board/arduino/portenta-x8/anx7625.h - cp ${WORKDIR}/board/anx7625.c ${S}/board/arduino/portenta-x8/anx7625.c - cp ${WORKDIR}/board/spl.c ${S}/board/arduino/portenta-x8/spl.c - cp ${WORKDIR}/board/lpddr4_timing.c ${S}/board/arduino/portenta-x8/lpddr4_timing.c - cp ${WORKDIR}/board/portenta-x8.c ${S}/board/arduino/portenta-x8/portenta-x8.c - cp ${WORKDIR}/board/mmc.c ${S}/board/arduino/portenta-x8/mmc.c -} - do_override_files_portenta_x9 () { + bbwarn Overriding files for ${MACHINE} + # Override Makefile cp ${WORKDIR}/Makefile ${S}/arch/arm/dts/Makefile - # @TODO: skip ecc defconfig if not necessary + # @TODO: inspect UBOOT_CONFIG_BASENAME for defconfig in use cp ${WORKDIR}/portenta-x9_defconfig ${S}/configs/imx93_11x11_evk_defconfig cp ${WORKDIR}/portenta-x9_inline_ecc_defconfig ${S}/configs/imx93_11x11_evk_inline_ecc_defconfig @@ -76,9 +81,51 @@ do_override_files_portenta_x9 () { cp ${WORKDIR}/portenta-x9.h ${S}/include/configs/imx93_evk.h } +SRC_URI:append:imx8mp-astrial = " \ + file://Makefile \ + file://imx8mp_astrial_defconfig \ + file://imx8mp_astrial_inline_ecc_defconfig \ + file://imx8mp_astrial_ndm_defconfig \ + file://imx8mp-astrial.dts \ + file://imx8mp-astrial-u-boot.dtsi \ + file://imx8mp_astrial.c \ + file://imx8mp-astrial_lpddr4_timing.c \ + file://imx8mp-astrial_lpddr4_timing_ndm.c \ + file://imx8mp-astrial_spl.c \ + file://imx8mp_astrial.h \ +" + +do_override_files_imx8mp_astrial () { + bbwarn Overriding files for ${MACHINE} + + # Override Makefile + cp ${WORKDIR}/Makefile ${S}/arch/arm/dts/Makefile + + # @TODO: inspect UBOOT_CONFIG_BASENAME for defconfig in use. + # The modes ECC and NDM are NAND-specific + cp ${WORKDIR}/imx8mp_astrial_defconfig ${S}/configs/imx8mp_evk_defconfig + cp ${WORKDIR}/imx8mp_astrial_ndm_defconfig ${S}/configs/imx8mp_evk_ndm_defconfig + cp ${WORKDIR}/imx8mp_astrial_inline_ecc_defconfig ${S}/configs/imx8mp_evk_inline_ecc_defconfig + + cp ${WORKDIR}/imx8mp-astrial.dts ${S}/arch/arm/dts/imx8mp-evk.dts + + # @TODO: u-boot auto-includes the *-u-boot.dtsi prepending MACHINE to the board devicetree + # see scripts/Makefile.lib, so should never be included directly from board devicetree + cp ${WORKDIR}/imx8mp-astrial-u-boot.dtsi ${S}/arch/arm/dts/imx8mp-evk-u-boot.dtsi + + cp ${WORKDIR}/imx8mp_astrial.c ${S}/board/freescale/imx8mp_evk/imx8mp_evk.c + cp ${WORKDIR}/imx8mp-astrial_lpddr4_timing.c ${S}/board/freescale/imx8mp_evk/lpddr4_timing.c + cp ${WORKDIR}/imx8mp-astrial_lpddr4_timing_ndm.c ${S}/board/freescale/imx8mp_evk/lpddr4_timing_ndm.c + cp ${WORKDIR}/imx8mp-astrial_spl.c ${S}/board/freescale/imx8mp_evk/spl.c + + cp ${WORKDIR}/imx8mp_astrial.h ${S}/include/configs/imx8mp_evk.h +} + python () { if d.getVar('MACHINE') == 'portenta-x8': bb.build.addtask('do_override_files_portenta_x8', 'do_configure', 'do_patch', d) elif d.getVar('MACHINE') == 'portenta-x9': bb.build.addtask('do_override_files_portenta_x9', 'do_configure', 'do_patch', d) + elif d.getVar('MACHINE') == 'imx8mp-astrial': + bb.build.addtask('do_override_files_imx8mp_astrial', 'do_configure', 'do_patch', d) } diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino.bb b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino.bb index 0bdba37..f534162 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino.bb +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino.bb @@ -9,8 +9,8 @@ UENV_FILE = "uEnv.txt.in" BOOTCMD_FILE = "boot.cmd.in" SRC_URI += " \ - file://${UENV_FILE} \ - file://${BOOTCMD_FILE} \ + file://${MACHINE}/${UENV_FILE} \ + file://${MACHINE}/${BOOTCMD_FILE} \ " KERNEL_BOOTCMD ??= "bootz" @@ -22,7 +22,7 @@ do_configure[noexec] = "1" do_compile[noexec] = "1" do_mkimage() { - mkimage -A arm -T script -C none -n "Arduino boot script" -d ${WORKDIR}/${BOOTCMD_FILE} ${B}/boot.scr + mkimage -A arm -T script -C none -n "Arduino boot script" -d ${WORKDIR}/${MACHINE}/${BOOTCMD_FILE} ${B}/boot.scr } addtask mkimage after do_compile before do_install @@ -30,7 +30,7 @@ addtask mkimage after do_compile before do_install do_install() { install -d ${D}/boot install -m 0644 ${B}/boot.scr ${D}/boot/boot.scr - install -m 0644 ${WORKDIR}/${UENV_FILE} ${D}/boot/uEnv.txt + install -m 0644 ${WORKDIR}/${MACHINE}/${UENV_FILE} ${D}/boot/uEnv.txt } do_deploy() { @@ -52,4 +52,4 @@ PROVIDES += "u-boot-default-script" PACKAGE_ARCH = "${MACHINE_ARCH}" -COMPATIBLE_MACHINE = "(portenta-x9)" +COMPATIBLE_MACHINE = "(portenta-x8|portenta-x9|imx8mp-astrial)" diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/boot.cmd.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/boot.cmd.in new file mode 100644 index 0000000..47af1b2 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/boot.cmd.in @@ -0,0 +1,56 @@ +# Import custom env file +setenv mmcdev ${emmc_dev} +setenv bootenv uEnv.txt +setenv bootdir /boot +setenv loadbootenv 'load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootenv}' +setenv importbootenv 'echo Importing environment from mmc ...; env import -t -r $loadaddr $filesize' +run loadbootenv +run importbootenv + +# Set environment variables +# Note: loadaddr - fdt_addr = 60 MB +setenv fdt_addr 0x44000000 +setenv image Image +setenv loadaddr 0x40400000 +setenv loadimage 'load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${image}' +setenv loadfdt 'echo fdt_file=${fdt_file}; load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${bootdir}/devicetree/${fdt_file}' + +setenv devtype mmc +setenv ovlload ext4load +setenv ovltype mmc +setenv ovlpart ${mmcpart} +setenv ovldev ${mmcdev} +setenv ovlpath ${bootdir}/devicetree +setenv fdtovaddr 0x48000000 +setenv ovlrm ${rmlist} +setenv remove_nodes 'for node in ${ovlrm}; do \ + echo Removing node ${node}; \ + fdt rm ${node}; \ + done' +setenv overlays ${ovlist} +setenv bootcmd_ovl 'fdt addr ${fdt_addr}; \ + run remove_nodes; \ + fdt resize 0x${filesize}; \ + for ov in ${overlays}; do \ + echo Overlaying ${ov}...; \ + ${ovlload} ${ovltype} ${ovldev}:${ovlpart} ${fdtovaddr} ${ovlpath}/${ov}.dtbo && \ + fdt apply ${fdtovaddr}; \ + done' + +# Load the kernel image and device tree blob +echo "Using kernel image ${image}" +run loadimage +echo "Using root devicetree ${fdt_file}" +run loadfdt + +# Apply overlays +#run bootcmd_ovl + +# Set boot arguments (bootargs) +setenv console 'ttymxc0,115200 earlycon' +setenv mmcblk ${mmcdev} +setenv mmcroot /dev/mmcblk${mmcblk}p${mmcpart} +run mmcargs + +# Boot the kernel +booti ${loadaddr} - ${fdt_addr} diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/uEnv.txt.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/uEnv.txt.in new file mode 100644 index 0000000..471b6e4 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/imx8mp-astrial/uEnv.txt.in @@ -0,0 +1,18 @@ +# Define root devicetree file available in /boot/devicetree +fdt_file=imx8mp-astrial.dtb + +# Define devicetree nodes to be removed (optional) +# Example: rmlist='/soc@0/bus@32c00000/usb@32e40000/port/endpoint' +rmlist='' + +# Define devicetree overlay list (optional) +# Example: ovlist='overlay1 overlay2 overlay3' +ovlist='' + +# Init: linuxrc +#rdinit=/linuxrc + +# Init: systemd +rdinit=/sbin/init + +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} rdinit=${rdinit} clk_ignore_unused rootwait rw diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/boot.cmd.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/boot.cmd.in new file mode 100644 index 0000000..e89e537 --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/boot.cmd.in @@ -0,0 +1,56 @@ +# Import custom env file +setenv mmcdev ${emmc_dev} +setenv bootenv uEnv.txt +setenv bootdir /boot +setenv loadbootenv 'load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootenv}' +setenv importbootenv 'echo Importing environment from mmc ...; env import -t -r $loadaddr $filesize' +run loadbootenv +run importbootenv + +# Set environment variables +# Note: loadaddr - fdt_addr = 60 MB +setenv fdt_addr 0x44000000 +setenv image Image +setenv loadaddr 0x40400000 +setenv loadimage 'load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${image}' +setenv loadfdt 'echo fdt_file=${fdt_file}; load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${bootdir}/devicetree/${fdt_file}' + +setenv devtype mmc +setenv ovlload ext4load +setenv ovltype mmc +setenv ovlpart ${mmcpart} +setenv ovldev ${mmcdev} +setenv ovlpath ${bootdir}/devicetree +setenv fdtovaddr 0x48000000 +setenv ovlrm ${rmlist} +setenv remove_nodes 'for node in ${ovlrm}; do \ + echo Removing node ${node}; \ + fdt rm ${node}; \ + done' +setenv overlays ${ovlist} +setenv bootcmd_ovl 'fdt addr ${fdt_addr}; \ + run remove_nodes; \ + fdt resize 0x${filesize}; \ + for ov in ${overlays}; do \ + echo Overlaying ${ov}...; \ + ${ovlload} ${ovltype} ${ovldev}:${ovlpart} ${fdtovaddr} ${ovlpath}/${ov}.dtbo && \ + fdt apply ${fdtovaddr}; \ + done' + +# Load the kernel image and device tree blob +echo "Using kernel image ${image}" +run loadimage +echo "Using root devicetree ${fdt_file}" +run loadfdt + +# Apply overlays +run bootcmd_ovl + +# Set boot arguments (bootargs) +setenv console 'ttymxc2,115200 earlycon' +setenv mmcblk ${mmcdev} +setenv mmcroot /dev/mmcblk${mmcblk}p${mmcpart} +run mmcargs + +# Boot the kernel +booti ${loadaddr} - ${fdt_addr} diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/uEnv.txt.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/uEnv.txt.in new file mode 100644 index 0000000..9537ebe --- /dev/null +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x8/uEnv.txt.in @@ -0,0 +1,18 @@ +# Define root devicetree file available in /boot/devicetree +fdt_file=arduino_portenta-x8.dtb + +# Define devicetree nodes to be removed (optional) +# Example: rmlist='/soc@0/bus@32c00000/usb@32e40000/port/endpoint' +rmlist='' + +# Define devicetree overlay list (optional) +# Example: ovlist='overlay1 overlay2 overlay3' +ovlist='' + +# Init: linuxrc +#rdinit=/linuxrc + +# Init: systemd +rdinit=/sbin/init + +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} rdinit=${rdinit} clk_ignore_unused rootwait rw diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/boot.cmd.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x9/boot.cmd.in similarity index 98% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/boot.cmd.in rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x9/boot.cmd.in index 9810669..71b9053 100644 --- a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/boot.cmd.in +++ b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x9/boot.cmd.in @@ -21,7 +21,7 @@ setenv ovltype mmc setenv ovlpart ${mmcpart} setenv ovldev ${mmcdev} setenv ovlpath ${bootdir}/devicetree -setenv fdtovaddr 0x83600000 +setenv fdtovaddr 0x88000000 setenv ovlrm ${rmlist} setenv remove_nodes 'for node in ${ovlrm}; do \ echo Removing node ${node}; \ diff --git a/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/uEnv.txt.in b/meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x9/uEnv.txt.in similarity index 100% rename from meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/uEnv.txt.in rename to meta-arduino-bsp/recipes-bsp/u-boot/u-boot-script-arduino/portenta-x9/uEnv.txt.in diff --git a/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager/NetworkManager.conf b/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager/NetworkManager.conf new file mode 100644 index 0000000..7c6a501 --- /dev/null +++ b/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager/NetworkManager.conf @@ -0,0 +1,2 @@ +[ifupdown] +managed=true diff --git a/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager_%.bbappend b/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager_%.bbappend new file mode 100644 index 0000000..8b22fb9 --- /dev/null +++ b/meta-arduino-bsp/recipes-connectivity/networkmanager/networkmanager_%.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" + +SRC_URI:append = " \ + file://NetworkManager.conf \ +" + +do_install:append() { + install -Dm 0644 ${WORKDIR}/NetworkManager.conf ${D}${sysconfdir}/NetworkManager/NetworkManager.conf +} \ No newline at end of file diff --git a/meta-arduino-bsp/recipes-devtools/openocd/files/OPENOCD-001-fix-libgpiod-required-version-lower-than-2_0.patch b/meta-arduino-bsp/recipes-devtools/openocd/files/OPENOCD-001-fix-libgpiod-required-version-lower-than-2_0.patch new file mode 100644 index 0000000..08dfb50 --- /dev/null +++ b/meta-arduino-bsp/recipes-devtools/openocd/files/OPENOCD-001-fix-libgpiod-required-version-lower-than-2_0.patch @@ -0,0 +1,600 @@ +From e6a2c12f41c9d1131b980c47af7517b4a5aca110 Mon Sep 17 00:00:00 2001 +From: Michael Heimpold +Date: Thu, 21 Mar 2024 07:34:18 +0100 +Subject: [PATCH] drivers/linuxgpiodv2: introduce new driver for libgpiod v2 + API + +This driver is a copy of the existing linuxgpiod driver but adapted +to the newer v2 API of libgpiod. + +I've chosen to add it in parallel to the existing driver so that it +is possible to have releases with support for both. + +I decided to make a dedicated new module to prevent having a lot of +ifdef-ery inside the C file itself - in my eyes, the small amount of +additionl makefile magic is simpler. + +The version of libgpiod is detected during configure time based on +the pkg-config version detection since the library itself does not +provide any defines or similar stuff. + +Change-Id: Ifac92b282ff8e83b2aebbcd75b61a554c9d36937 +Signed-off-by: Michael Heimpold +--- + configure.ac | 16 +- + src/jtag/drivers/Makefile.am | 4 + + src/jtag/drivers/linuxgpiodv2.c | 520 ++++++++++++++++++++++++++++++++ + 3 files changed, 536 insertions(+), 4 deletions(-) + create mode 100644 src/jtag/drivers/linuxgpiodv2.c + +diff --git a/configure.ac b/configure.ac +index 3152c1526..142a272c0 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -652,11 +652,19 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [ + PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no]) + ]) + +-PKG_CHECK_MODULES([LIBGPIOD], [libgpiod < 2.0], [ ++PKG_CHECK_MODULES([LIBGPIOD], [libgpiod >= 2.0], [ + use_libgpiod=yes +- PKG_CHECK_EXISTS([libgpiod >= 1.5], +- [AC_DEFINE([HAVE_LIBGPIOD1_FLAGS_BIAS], [1], [define if libgpiod v1 has line request flags bias])]) +-], [use_libgpiod=no]) ++ is_libgpiodv2=yes ++], [ ++ PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [ ++ use_libgpiod=yes ++ is_libgpiodv2=no ++ ], [ ++ use_libgpiod=no ++ is_libgpiodv2=no ++ ]) ++]) ++AM_CONDITIONAL([LINUXGPIODV2], [test x$is_libgpiodv2 = xyes]) + + PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2], + [use_libjaylink=yes], [use_libjaylink=no]) +diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am +index b0dd8e3ad..5b1508d83 100644 +--- a/src/jtag/drivers/Makefile.am ++++ b/src/jtag/drivers/Makefile.am +@@ -72,8 +72,12 @@ if FTDI + DRIVERFILES += %D%/ftdi.c %D%/mpsse.c + endif + if LINUXGPIOD ++if LINUXGPIODV2 ++DRIVERFILES += %D%/linuxgpiodv2.c ++else + DRIVERFILES += %D%/linuxgpiod.c + endif ++endif + if JTAG_VPI + DRIVERFILES += %D%/jtag_vpi.c + endif +diff --git a/src/jtag/drivers/linuxgpiodv2.c b/src/jtag/drivers/linuxgpiodv2.c +new file mode 100644 +index 000000000..59850905a +--- /dev/null ++++ b/src/jtag/drivers/linuxgpiodv2.c +@@ -0,0 +1,520 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Bitbang driver for Linux GPIO descriptors through libgpiod ++ * using the library's v2 API. ++ * Copyright (C) 2024 Michael Heimpold ++ * ++ * Derived from linuxgpiod.c: ++ * Copyright (C) 2020 Antonio Borneo ++ * ++ * Which in turn was largely based on sysfsgpio driver: ++ * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au ++ * Copyright (C) 2014 by Jean-Christian de Rivaz ++ * Copyright (C) 2014 by Paul Fertser ++ */ ++ ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif ++ ++#include ++#include ++#include ++#include ++#include "bitbang.h" ++ ++static struct gpiod_chip *gpiod_chip[ADAPTER_GPIO_IDX_NUM] = {}; ++static struct gpiod_line_settings *gpiod_line_settings[ADAPTER_GPIO_IDX_NUM] = {}; ++static struct gpiod_line_config *gpiod_line_config[ADAPTER_GPIO_IDX_NUM] = {}; ++static struct gpiod_line_request *gpiod_line_request[ADAPTER_GPIO_IDX_NUM] = {}; ++ ++static int last_swclk; ++static int last_swdio; ++static bool last_stored; ++static bool swdio_input; ++ ++static const struct adapter_gpio_config *adapter_gpio_config; ++ ++/* Helper to get/set a single line */ ++static int linuxgpiod_line_get_value(enum adapter_gpio_config_index idx) ++{ ++ return gpiod_line_request_get_value(gpiod_line_request[idx], ++ adapter_gpio_config[idx].gpio_num); ++} ++ ++static int linuxgpiod_line_set_value(enum adapter_gpio_config_index idx, int value) ++{ ++ return gpiod_line_request_set_value(gpiod_line_request[idx], ++ adapter_gpio_config[idx].gpio_num, ++ value); ++} ++ ++/* ++ * Helper function to determine if gpio config is valid ++ * ++ * Assume here that there will be less than 10000 gpios per gpiochip, and less ++ * than 1000 gpiochips. ++ */ ++static bool is_gpio_config_valid(enum adapter_gpio_config_index idx) ++{ ++ return adapter_gpio_config[idx].chip_num < 1000 ++ && adapter_gpio_config[idx].gpio_num < 10000; ++} ++ ++/* Bitbang interface read of TDO */ ++static enum bb_value linuxgpiod_read(void) ++{ ++ int retval; ++ ++ retval = linuxgpiod_line_get_value(ADAPTER_GPIO_IDX_TDO); ++ if (retval < 0) { ++ LOG_WARNING("reading tdo failed"); ++ return 0; ++ } ++ ++ return retval ? BB_HIGH : BB_LOW; ++} ++ ++/* ++ * Bitbang interface write of TCK, TMS, TDI ++ * ++ * Seeing as this is the only function where the outputs are changed, ++ * we can cache the old value to avoid needlessly writing it. ++ */ ++static int linuxgpiod_write(int tck, int tms, int tdi) ++{ ++ static int last_tck; ++ static int last_tms; ++ static int last_tdi; ++ ++ static int first_time; ++ ++ int retval; ++ ++ if (!first_time) { ++ last_tck = !tck; ++ last_tms = !tms; ++ last_tdi = !tdi; ++ first_time = 1; ++ } ++ ++ if (tdi != last_tdi) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_TDI, tdi); ++ if (retval < 0) ++ LOG_WARNING("writing tdi failed"); ++ } ++ ++ if (tms != last_tms) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_TMS, tms); ++ if (retval < 0) ++ LOG_WARNING("writing tms failed"); ++ } ++ ++ /* write clk last */ ++ if (tck != last_tck) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_TCK, tck); ++ if (retval < 0) ++ LOG_WARNING("writing tck failed"); ++ } ++ ++ last_tdi = tdi; ++ last_tms = tms; ++ last_tck = tck; ++ ++ return ERROR_OK; ++} ++ ++static int linuxgpiod_swdio_read(void) ++{ ++ int retval; ++ ++ retval = linuxgpiod_line_get_value(ADAPTER_GPIO_IDX_SWDIO); ++ if (retval < 0) { ++ LOG_WARNING("Fail read swdio"); ++ return 0; ++ } ++ ++ return retval; ++} ++ ++static void linuxgpiod_swdio_drive(bool is_output) ++{ ++ int retval; ++ ++ if (is_output) { ++ if (gpiod_line_request[ADAPTER_GPIO_IDX_SWDIO_DIR]) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_SWDIO_DIR, 1); ++ if (retval < 0) ++ LOG_WARNING("Failed to set swdio_dir=1"); ++ } ++ ++ retval = gpiod_line_settings_set_direction(gpiod_line_settings[ADAPTER_GPIO_IDX_SWDIO], ++ GPIOD_LINE_DIRECTION_OUTPUT); ++ if (retval < 0) ++ LOG_WARNING("Failed to set new direction of swdio"); ++ ++ retval = gpiod_line_settings_set_output_value(gpiod_line_settings[ADAPTER_GPIO_IDX_SWDIO], ++ GPIOD_LINE_VALUE_ACTIVE); ++ if (retval < 0) ++ LOG_WARNING("Failed to set output value of swdio"); ++ ++ retval = gpiod_line_config_add_line_settings(gpiod_line_config[ADAPTER_GPIO_IDX_SWDIO], ++ &adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num, 1, ++ gpiod_line_settings[ADAPTER_GPIO_IDX_SWDIO]); ++ if (retval < 0) ++ LOG_WARNING("Failed to apply output configuration to swdio"); ++ ++ retval = gpiod_line_request_reconfigure_lines(gpiod_line_request[ADAPTER_GPIO_IDX_SWDIO], ++ gpiod_line_config[ADAPTER_GPIO_IDX_SWDIO]); ++ if (retval < 0) ++ LOG_WARNING("Failed to switch swdio to output"); ++ } else { ++ retval = gpiod_line_settings_set_direction(gpiod_line_settings[ADAPTER_GPIO_IDX_SWDIO], ++ GPIOD_LINE_DIRECTION_INPUT); ++ if (retval < 0) ++ LOG_WARNING("Failed to switch swdio to output"); ++ ++ retval = gpiod_line_config_add_line_settings(gpiod_line_config[ADAPTER_GPIO_IDX_SWDIO], ++ &adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].gpio_num, 1, ++ gpiod_line_settings[ADAPTER_GPIO_IDX_SWDIO]); ++ if (retval < 0) ++ LOG_WARNING("Failed to apply input configuration to swdio"); ++ ++ retval = gpiod_line_request_reconfigure_lines(gpiod_line_request[ADAPTER_GPIO_IDX_SWDIO], ++ gpiod_line_config[ADAPTER_GPIO_IDX_SWDIO]); ++ if (retval < 0) ++ LOG_WARNING("Failed to switch swdio to input"); ++ ++ if (gpiod_line_request[ADAPTER_GPIO_IDX_SWDIO_DIR]) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_SWDIO_DIR, 0); ++ if (retval < 0) ++ LOG_WARNING("Failed to set swdio_dir=0"); ++ } ++ } ++ ++ last_stored = false; ++ swdio_input = !is_output; ++} ++ ++static int linuxgpiod_swd_write(int swclk, int swdio) ++{ ++ int retval; ++ ++ if (!swdio_input) { ++ if (!last_stored || (swdio != last_swdio)) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_SWDIO, swdio); ++ if (retval < 0) ++ LOG_WARNING("Fail set swdio"); ++ } ++ } ++ ++ /* write swclk last */ ++ if (!last_stored || (swclk != last_swclk)) { ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_SWCLK, swclk); ++ if (retval < 0) ++ LOG_WARNING("Fail set swclk"); ++ } ++ ++ last_swdio = swdio; ++ last_swclk = swclk; ++ last_stored = true; ++ ++ return ERROR_OK; ++} ++ ++static int linuxgpiod_blink(bool on) ++{ ++ int retval; ++ ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_LED)) ++ return ERROR_OK; ++ ++ retval = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_LED, on); ++ if (retval < 0) ++ LOG_WARNING("Fail set led"); ++ return retval; ++} ++ ++static struct bitbang_interface linuxgpiod_bitbang = { ++ .read = linuxgpiod_read, ++ .write = linuxgpiod_write, ++ .swdio_read = linuxgpiod_swdio_read, ++ .swdio_drive = linuxgpiod_swdio_drive, ++ .swd_write = linuxgpiod_swd_write, ++ .blink = linuxgpiod_blink, ++}; ++ ++/* ++ * Bitbang interface to manipulate reset lines SRST and TRST ++ * ++ * (1) assert or (0) deassert reset lines ++ */ ++static int linuxgpiod_reset(int trst, int srst) ++{ ++ int retval1 = 0, retval2 = 0; ++ ++ LOG_DEBUG("linuxgpiod_reset"); ++ ++ /* ++ * active low behavior handled by "adaptor gpio" command and ++ * thus handled when requesting the line. ++ */ ++ if (gpiod_line_request[ADAPTER_GPIO_IDX_SRST]) { ++ retval1 = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_SRST, srst); ++ if (retval1 < 0) ++ LOG_WARNING("set srst value failed"); ++ } ++ ++ if (gpiod_line_request[ADAPTER_GPIO_IDX_TRST]) { ++ retval2 = linuxgpiod_line_set_value(ADAPTER_GPIO_IDX_TRST, trst); ++ if (retval2 < 0) ++ LOG_WARNING("set trst value failed"); ++ } ++ ++ return ((retval1 < 0) || (retval2 < 0)) ? ERROR_FAIL : ERROR_OK; ++} ++ ++static bool linuxgpiod_jtag_mode_possible(void) ++{ ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TCK)) ++ return false; ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TMS)) ++ return false; ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDI)) ++ return false; ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_TDO)) ++ return false; ++ return true; ++} ++ ++static bool linuxgpiod_swd_mode_possible(void) ++{ ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWCLK)) ++ return false; ++ if (!is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO)) ++ return false; ++ return true; ++} ++ ++static inline void helper_release(enum adapter_gpio_config_index idx) ++{ ++ if (gpiod_line_request[idx]) { ++ gpiod_line_request_release(gpiod_line_request[idx]); ++ gpiod_line_request[idx] = NULL; ++ } ++ if (gpiod_line_config[idx]) { ++ gpiod_line_config_free(gpiod_line_config[idx]); ++ gpiod_line_config[idx] = NULL; ++ } ++ if (gpiod_line_settings[idx]) { ++ gpiod_line_settings_free(gpiod_line_settings[idx]); ++ gpiod_line_settings[idx] = NULL; ++ } ++ if (gpiod_chip[idx]) { ++ gpiod_chip_close(gpiod_chip[idx]); ++ gpiod_chip[idx] = NULL; ++ } ++} ++ ++static int linuxgpiod_quit(void) ++{ ++ LOG_DEBUG("linuxgpiod_quit"); ++ for (int i = 0; i < ADAPTER_GPIO_IDX_NUM; ++i) ++ helper_release(i); ++ ++ return ERROR_OK; ++} ++ ++static struct gpiod_chip *gpiod_chip_open_by_number(unsigned int chip_num) ++{ ++ char chip_path[32]; ++ int l; ++ ++ l = snprintf(chip_path, sizeof(chip_path), "/dev/gpiochip%u", chip_num); ++ if (l < 0 || l >= (int)sizeof(chip_path)) ++ return NULL; ++ ++ return gpiod_chip_open(chip_path); ++} ++ ++static int helper_get_line(enum adapter_gpio_config_index idx) ++{ ++ struct gpiod_request_config *req_cfg = NULL; ++ int retval = -1; ++ ++ if (!is_gpio_config_valid(idx)) ++ return ERROR_OK; ++ ++ gpiod_chip[idx] = gpiod_chip_open_by_number(adapter_gpio_config[idx].chip_num); ++ if (!gpiod_chip[idx]) { ++ LOG_ERROR("Cannot open LinuxGPIOD chip %d for %s", adapter_gpio_config[idx].chip_num, ++ adapter_gpio_get_name(idx)); ++ return ERROR_JTAG_INIT_FAILED; ++ } ++ ++ gpiod_line_settings[idx] = gpiod_line_settings_new(); ++ gpiod_line_config[idx] = gpiod_line_config_new(); ++ req_cfg = gpiod_request_config_new(); ++ ++ if (!gpiod_line_settings[idx] || !gpiod_line_config[idx] || !req_cfg) { ++ LOG_ERROR("Cannot configure LinuxGPIOD line for %s", adapter_gpio_get_name(idx)); ++ return ERROR_JTAG_INIT_FAILED; ++ } ++ ++ gpiod_request_config_set_consumer(req_cfg, "OpenOCD"); ++ ++ switch (adapter_gpio_config[idx].init_state) { ++ case ADAPTER_GPIO_INIT_STATE_INPUT: ++ gpiod_line_settings_set_direction(gpiod_line_settings[idx], GPIOD_LINE_DIRECTION_INPUT); ++ break; ++ case ADAPTER_GPIO_INIT_STATE_INACTIVE: ++ gpiod_line_settings_set_direction(gpiod_line_settings[idx], GPIOD_LINE_DIRECTION_OUTPUT); ++ gpiod_line_settings_set_output_value(gpiod_line_settings[idx], GPIOD_LINE_VALUE_INACTIVE); ++ break; ++ case ADAPTER_GPIO_INIT_STATE_ACTIVE: ++ gpiod_line_settings_set_direction(gpiod_line_settings[idx], GPIOD_LINE_DIRECTION_OUTPUT); ++ gpiod_line_settings_set_output_value(gpiod_line_settings[idx], GPIOD_LINE_VALUE_ACTIVE); ++ break; ++ } ++ ++ if (adapter_gpio_config[idx].init_state != ADAPTER_GPIO_INIT_STATE_INPUT) { ++ switch (adapter_gpio_config[idx].drive) { ++ case ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL: ++ gpiod_line_settings_set_drive(gpiod_line_settings[idx], GPIOD_LINE_DRIVE_PUSH_PULL); ++ break; ++ case ADAPTER_GPIO_DRIVE_MODE_OPEN_DRAIN: ++ gpiod_line_settings_set_drive(gpiod_line_settings[idx], GPIOD_LINE_DRIVE_OPEN_DRAIN); ++ break; ++ case ADAPTER_GPIO_DRIVE_MODE_OPEN_SOURCE: ++ gpiod_line_settings_set_drive(gpiod_line_settings[idx], GPIOD_LINE_DRIVE_OPEN_SOURCE); ++ break; ++ } ++ } ++ ++ switch (adapter_gpio_config[idx].pull) { ++ case ADAPTER_GPIO_PULL_NONE: ++#ifdef GPIOD_LINE_BIAS_DISABLED ++ gpiod_line_settings_set_bias(gpiod_line_settings[idx], GPIOD_LINE_BIAS_DISABLED); ++#endif ++ break; ++ case ADAPTER_GPIO_PULL_UP: ++#ifdef GPIOD_LINE_BIAS_PULL_UP ++ gpiod_line_settings_set_bias(gpiod_line_settings[idx], GPIOD_LINE_BIAS_PULL_UP); ++#else ++ LOG_WARNING("linuxgpiodv2: ignoring request for pull-up on %s: not supported by gpiod v%s", ++ adapter_gpio_get_name(idx), gpiod_api_version()); ++#endif ++ break; ++ case ADAPTER_GPIO_PULL_DOWN: ++#ifdef GPIOD_LINE_BIAS_PULL_DOWN ++ gpiod_line_settings_set_bias(gpiod_line_settings[idx], GPIOD_LINE_BIAS_PULL_DOWN); ++#else ++ LOG_WARNING("linuxgpiodv2: ignoring request for pull-down on %s: not supported by gpiod v%s", ++ adapter_gpio_get_name(idx), gpiod_api_version()); ++#endif ++ break; ++ } ++ ++ gpiod_line_settings_set_active_low(gpiod_line_settings[idx], adapter_gpio_config[idx].active_low); ++ ++ retval = gpiod_line_config_add_line_settings(gpiod_line_config[idx], ++ &adapter_gpio_config[idx].gpio_num, 1, gpiod_line_settings[idx]); ++ if (retval < 0) { ++ gpiod_request_config_free(req_cfg); ++ LOG_ERROR("Error configuring gpio line %s", adapter_gpio_get_name(idx)); ++ return ERROR_JTAG_INIT_FAILED; ++ } ++ ++ gpiod_line_request[idx] = gpiod_chip_request_lines(gpiod_chip[idx], req_cfg, gpiod_line_config[idx]); ++ gpiod_request_config_free(req_cfg); ++ ++ if (!gpiod_line_request[idx]) { ++ LOG_ERROR("Error requesting gpio line %s", adapter_gpio_get_name(idx)); ++ return ERROR_JTAG_INIT_FAILED; ++ } ++ ++ return ERROR_OK; ++} ++ ++static int linuxgpiod_init(void) ++{ ++ LOG_INFO("Linux GPIOD JTAG/SWD bitbang driver (libgpiod v2)"); ++ ++ bitbang_interface = &linuxgpiod_bitbang; ++ adapter_gpio_config = adapter_gpio_get_config(); ++ ++ /* ++ * Configure JTAG/SWD signals. Default directions and initial states are handled ++ * by adapter.c and "adapter gpio" command. ++ */ ++ ++ if (transport_is_jtag()) { ++ if (!linuxgpiod_jtag_mode_possible()) { ++ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode"); ++ goto out_error; ++ } ++ ++ if (helper_get_line(ADAPTER_GPIO_IDX_TDO) != ERROR_OK || ++ helper_get_line(ADAPTER_GPIO_IDX_TDI) != ERROR_OK || ++ helper_get_line(ADAPTER_GPIO_IDX_TCK) != ERROR_OK || ++ helper_get_line(ADAPTER_GPIO_IDX_TMS) != ERROR_OK || ++ helper_get_line(ADAPTER_GPIO_IDX_TRST) != ERROR_OK) ++ goto out_error; ++ } ++ ++ if (transport_is_swd()) { ++ int retval1, retval2; ++ if (!linuxgpiod_swd_mode_possible()) { ++ LOG_ERROR("Require swclk and swdio gpio for SWD mode"); ++ goto out_error; ++ } ++ ++ /* ++ * swdio and its buffer should be initialized in the order that prevents ++ * two outputs from being connected together. This will occur if the ++ * swdio GPIO is configured as an output while the external buffer is ++ * configured to send the swdio signal from the target to the GPIO. ++ */ ++ if (adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO].init_state == ADAPTER_GPIO_INIT_STATE_INPUT) { ++ retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO); ++ retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR); ++ } else { ++ retval1 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO_DIR); ++ retval2 = helper_get_line(ADAPTER_GPIO_IDX_SWDIO); ++ } ++ if (retval1 != ERROR_OK || retval2 != ERROR_OK) ++ goto out_error; ++ ++ if (helper_get_line(ADAPTER_GPIO_IDX_SWCLK) != ERROR_OK) ++ goto out_error; ++ } ++ ++ if (helper_get_line(ADAPTER_GPIO_IDX_SRST) != ERROR_OK || ++ helper_get_line(ADAPTER_GPIO_IDX_LED) != ERROR_OK) ++ goto out_error; ++ ++ return ERROR_OK; ++ ++out_error: ++ linuxgpiod_quit(); ++ ++ return ERROR_JTAG_INIT_FAILED; ++} ++ ++static struct jtag_interface linuxgpiod_interface = { ++ .supported = DEBUG_CAP_TMS_SEQ, ++ .execute_queue = bitbang_execute_queue, ++}; ++ ++struct adapter_driver linuxgpiod_adapter_driver = { ++ .name = "linuxgpiod", ++ .transport_ids = TRANSPORT_SWD | TRANSPORT_JTAG, ++ .transport_preferred_id = TRANSPORT_SWD, ++ ++ .init = linuxgpiod_init, ++ .quit = linuxgpiod_quit, ++ .reset = linuxgpiod_reset, ++ ++ .jtag_ops = &linuxgpiod_interface, ++ .swd_ops = &bitbang_swd, ++}; diff --git a/meta-arduino-bsp/recipes-devtools/openocd/openocd_%.bbappend b/meta-arduino-bsp/recipes-devtools/openocd/openocd_%.bbappend index ae3788d..b0453a6 100644 --- a/meta-arduino-bsp/recipes-devtools/openocd/openocd_%.bbappend +++ b/meta-arduino-bsp/recipes-devtools/openocd/openocd_%.bbappend @@ -1,5 +1,13 @@ -EXTRA_OECONF:append:portenta-x8 = " --enable-imx_gpio" -PACKAGECONFIG:append:portenta-x8 = " sysfsgpio" +FILESEXTRAPATHS:prepend := "${THISDIR}:" + +SRC_URI:append:portenta-x8 = " \ + file://files/OPENOCD-001-fix-libgpiod-required-version-lower-than-2_0.patch \ +" + +SRCREV_openocd:portenta-x8 = "4fe57a0c197158958c7cc295002504d6434d4777" + +DEPENDS:append:portenta-x8 = " libgpiod" + +EXTRA_OECONF:append:portenta-x8 = " --enable-imx_gpio --enable-linuxgpiod --enable-internal-jimtcl" +PACKAGECONFIG:remove:portenta-x8 = " sysfsgpio" -EXTRA_OECONF:append:portenta-x9 = " --enable-imx_gpio" -PACKAGECONFIG:append:portenta-x9 = " sysfsgpio" diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/anx7625/anx7625.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/anx7625/anx7625.c index 925c431..1b1384b 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/anx7625/anx7625.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/anx7625/anx7625.c @@ -2591,17 +2591,27 @@ static int anx7625_apply_pending_early_init_config(struct anx7625_data *ctx) } #endif -static int anx7625_i2c_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id anx7625_id[] = { + {"anx7625", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, anx7625_id); + +static int anx7625_i2c_probe(struct i2c_client *client) { struct anx7625_data *platform; struct anx7625_platform_data *pdata; - int ret = 0; struct device *dev = &client->dev; struct regulator *regulator; + const struct i2c_device_id *id = i2c_match_id(anx7625_id, client); + int ret = 0; DRM_DEV_DEBUG_DRIVER(dev, "anx probing ...\n"); + if (!id) + return -ENODEV; + regulator = devm_regulator_get(dev, "vdda"); if (IS_ERR(regulator)) { if (PTR_ERR(regulator) == -EPROBE_DEFER) { @@ -2769,13 +2779,6 @@ static void anx7625_i2c_remove(struct i2c_client *client) kfree(platform); } -static const struct i2c_device_id anx7625_id[] = { - {"anx7625", 0}, - {} -}; - -MODULE_DEVICE_TABLE(i2c, anx7625_id); - #ifdef CONFIG_OF static const struct of_device_id anx_match_table[] = { {.compatible = "analogix,anx7625",}, @@ -2792,7 +2795,6 @@ static struct i2c_driver anx7625_driver = { }, .probe = anx7625_i2c_probe, .remove = anx7625_i2c_remove, - .id_table = anx7625_id, }; diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/atmel-mxt-ts/atmel_mxt_ts.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/atmel-mxt-ts/atmel_mxt_ts.c index 0690bf7..85d92fa 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/atmel-mxt-ts/atmel_mxt_ts.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/atmel-mxt-ts/atmel_mxt_ts.c @@ -3082,11 +3082,25 @@ static const struct dmi_system_id chromebook_T9_suspend_dmi[] = { { } }; -static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) +static const struct i2c_device_id mxt_id[] = { + { "qt602240_ts", 0 }, + { "atmel_mxt_ts", 0 }, + { "atmel_mxt_tp", 0 }, + { "maxtouch", 0 }, + { "mXT224", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mxt_id); + +static int mxt_probe(struct i2c_client *client) { struct mxt_data *data; int error; + const struct i2c_device_id *id = i2c_match_id(mxt_id, client); + + if (!id) + return -ENODEV; /* * Ignore devices that do not have device properties attached to * them, as we need help determining whether we are dealing with @@ -3251,15 +3265,6 @@ static const struct acpi_device_id mxt_acpi_id[] = { MODULE_DEVICE_TABLE(acpi, mxt_acpi_id); #endif -static const struct i2c_device_id mxt_id[] = { - { "qt602240_ts", 0 }, - { "atmel_mxt_ts", 0 }, - { "atmel_mxt_tp", 0 }, - { "maxtouch", 0 }, - { "mXT224", 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, mxt_id); static struct i2c_driver mxt_driver = { .driver = { diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/bq24195/bq24190_charger.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/bq24195/bq24190_charger.c index 375ff14..e7fa022 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/bq24195/bq24190_charger.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/bq24195/bq24190_charger.c @@ -1781,15 +1781,28 @@ static int bq24190_get_config(struct bq24190_dev_info *bdi) return 0; } -static int bq24190_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static const struct i2c_device_id bq24190_i2c_ids[] = { + { "bq24190" }, + { "bq24192" }, + { "bq24192i" }, + { "bq24196" }, + { "bq24195" }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, bq24190_i2c_ids); + +static int bq24190_probe(struct i2c_client *client) { struct i2c_adapter *adapter = client->adapter; struct device *dev = &client->dev; struct power_supply_config charger_cfg = {}, battery_cfg = {}; struct bq24190_dev_info *bdi; int ret; + const struct i2c_device_id *id = i2c_match_id(bq24190_i2c_ids, client); + if (!id) + return -ENODEV; + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { dev_err(dev, "No support for SMBUS_BYTE_DATA\n"); return -ENODEV; @@ -2028,15 +2041,6 @@ static const struct dev_pm_ops bq24190_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(bq24190_pm_suspend, bq24190_pm_resume) }; -static const struct i2c_device_id bq24190_i2c_ids[] = { - { "bq24190" }, - { "bq24192" }, - { "bq24192i" }, - { "bq24196" }, - { "bq24195" }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, bq24190_i2c_ids); static const struct of_device_id bq24190_of_match[] = { { .compatible = "ti,bq24190", }, diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/cs42l52/cs42l52.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/cs42l52/cs42l52.c index 58ba7c1..ccec0c3 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/cs42l52/cs42l52.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/cs42l52/cs42l52.c @@ -1252,7 +1252,7 @@ static struct i2c_driver cs42l52_i2c_driver = { .of_match_table = cs42l52_of_match, }, .id_table = cs42l52_id, - .probe_new = cs42l52_i2c_probe, + .probe = cs42l52_i2c_probe, }; module_i2c_driver(cs42l52_i2c_driver); diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver.bb b/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver.bb index 9c71e31..6ce6c9e 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver.bb +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver.bb @@ -9,10 +9,10 @@ SRC_URI = " \ git://github.com/hailo-ai/hailort-drivers.git;branch=master;protocol=https \ file://0001-OE-fix-Makefile.patch;patchdir=../../ \ " -SRCREV = "43e8a9a575654c773edf95789f93cde40c708a6a" +SRCREV = "64897376cd67954ff497e194d6ca76d67f404b26" S = "${WORKDIR}/git/linux/pcie" -PV = "v4.17.1" +PV = "v4.21.0" RPROVIDES_${PN} += "kernel-module-hailo-pcie-driver" diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver/0001-OE-fix-Makefile.patch b/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver/0001-OE-fix-Makefile.patch index 558cbba..d06ae9d 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver/0001-OE-fix-Makefile.patch +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/hailo-pcie-driver/0001-OE-fix-Makefile.patch @@ -1,10 +1,10 @@ diff --git a/linux/pcie/Makefile b/linux/pcie/Makefile -index 705d15d..56e0e61 100755 +index c654b1f..5ba535e 100755 --- a/linux/pcie/Makefile +++ b/linux/pcie/Makefile -@@ -65,99 +65,20 @@ PWD := $(shell pwd) - PUBLIC_INC_DIR = $(BUILD_DIR)/include - PUBLIC_INC_FILE = $(PUBLIC_INC_DIR)/hailo_pcie_ioctl.h +@@ -62,98 +62,20 @@ DEPMOD ?= depmod + + PWD := $(shell pwd) -default: help - @@ -20,7 +20,6 @@ index 705d15d..56e0e61 100755 - $(Q)echo "* " - $(Q)echo "* target: " - $(Q)echo "* all Generate the ko file in $(BUILD_DIR)/[release|debug]/$(ARCH) " -- $(Q)echo "* copy the public include files in $(PUBLIC_INC_DIR) " - $(Q)echo "* " - $(Q)echo "* clean Delete the generated files " - $(Q)echo "* Delete $(BUILD_DIR) directory " @@ -34,18 +33,18 @@ index 705d15d..56e0e61 100755 - $(Q)echo "* help: Display this help " - $(Q)echo "******************************************************************************" - --all: $(PUBLIC_INC_FILE) $(TARGET_DIR) +-print-versions: +- $(Q)kernelver="$(make -s -C $(KERNEL_DIR) kernelversion || echo \"unknown\")" +- $(Q)echo "******************************************************************************" +- $(Q)echo "Kernel version: $(kernelver)" +- $(Q)echo "******************************************************************************" +- +-all: $(TARGET_DIR) print-versions - $(Q)$(MAKE) -C $(KERNEL_DIR) M=$(PWD) $(GDB_FLAG) $(USER_FLAGS) modules - $(Q)cp $(DRIVER_NAME) $(TARGET_DIR) - -$(TARGET_DIR): - $(Q)mkdir -p $@ -- --$(PUBLIC_INC_DIR): -- $(Q)mkdir -p $@ -- --$(PUBLIC_INC_FILE): $(PUBLIC_INC_DIR) -- $(Q)cp -f $(PWD)/include/* $(PUBLIC_INC_DIR)/ +all: + $(MAKE) -C $(KERNEL_SRC) M=$(PWD) modules diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/imx219/imx219.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/imx219/imx219.c index 63a9af3..bc2be2e 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/imx219/imx219.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/imx219/imx219.c @@ -1559,7 +1559,7 @@ static struct i2c_driver imx219_i2c_driver = { .of_match_table = imx219_dt_ids, .pm = &imx219_pm_ops, }, - .probe_new = imx219_probe, + .probe = imx219_probe, .remove = imx219_remove, }; diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/imx477/imx477.c b/meta-arduino-bsp/recipes-kernel/kernel-modules/imx477/imx477.c index aeec77b..892e75f 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/imx477/imx477.c +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/imx477/imx477.c @@ -2308,7 +2308,7 @@ static struct i2c_driver imx477_i2c_driver = { .of_match_table = imx477_dt_ids, .pm = &imx477_pm_ops, }, - .probe_new = imx477_probe, + .probe = imx477_probe, .remove = imx477_remove, }; diff --git a/meta-arduino-bsp/recipes-kernel/kernel-modules/x8h7.bb b/meta-arduino-bsp/recipes-kernel/kernel-modules/x8h7.bb index 2d70070..86d872e 100644 --- a/meta-arduino-bsp/recipes-kernel/kernel-modules/x8h7.bb +++ b/meta-arduino-bsp/recipes-kernel/kernel-modules/x8h7.bb @@ -8,9 +8,9 @@ PR = "r1" PV = "0.1" SRC_URI = " \ - git://github.com/arduino/portentax8-x8h7.git;branch=main;protocol=https \ + git://github.com/arduino/portentax8-x8h7.git;branch=linux-imx-lf-6.6.y;protocol=https \ " -SRCREV = "c0b3550691d234c043b5cd69b36275154cb19a8f" +SRCREV = "${AUTOREV}" S = "${WORKDIR}/git" diff --git a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-arduino-portenta-x8-stm32h7_git.bb b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-arduino-portenta-x8-stm32h7_git.bb index 04ea1b3..6d09114 100644 --- a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-arduino-portenta-x8-stm32h7_git.bb +++ b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-arduino-portenta-x8-stm32h7_git.bb @@ -9,15 +9,15 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" PACKAGE_ARCH = "${MACHINE_ARCH}" SRC_URI = " \ - git://github.com/arduino/portentam8-stm32h7-fw.git;protocol=https;branch=master \ + git://github.com/arduino/portentam8-stm32h7-fw.git;protocol=https;branch=linux-imx-lf-6.6.y \ file://stm32h7-program.service \ file://m4-led-forwarder.service \ file://m4_led_forwarder \ file://monitor-m4-elf-file.path \ file://monitor-m4-elf-file.service \ " -SRCREV = "${AUTOREV}" -PV = "0.0.3" +SRCREV = "ae5dea0a40a8f212e4718a59b4c937a0d4a75d08" +PV = "0.0.5" S = "${WORKDIR}/git" @@ -90,4 +90,4 @@ DEPENDS += " \ " COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE:portenta-mx8mm = ".*" +COMPATIBLE_MACHINE:portenta-x8 = ".*" diff --git a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-bt-patch_git.bb b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-bt-patch_git.bb index e20fecc..b0365e6 100644 --- a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-bt-patch_git.bb +++ b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-bt-patch_git.bb @@ -48,4 +48,4 @@ RREPLACES:${PN} = "\ " COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE:portenta-mx8mm = ".*" +COMPATIBLE_MACHINE:portenta-x8 = ".*" diff --git a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-fw_git.bb b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-fw_git.bb index 32bedf7..8e1aa38 100644 --- a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-fw_git.bb +++ b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-fw_git.bb @@ -29,4 +29,4 @@ FILES:${PN} = " \ " COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE:portenta-mx8mm = ".*" +COMPATIBLE_MACHINE:portenta-x8 = ".*" diff --git a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-nvram_git.bb b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-nvram_git.bb index 7558186..5c75cad 100644 --- a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-nvram_git.bb +++ b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-nvram_git.bb @@ -27,4 +27,4 @@ FILES:${PN} = " \ " COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE:portenta-mx8mm = ".*" +COMPATIBLE_MACHINE:portenta-x8 = ".*" diff --git a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-utils-imx64_git.bb b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-utils-imx64_git.bb index e0a97e0..532d49c 100644 --- a/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-utils-imx64_git.bb +++ b/meta-arduino-bsp/recipes-kernel/linux-firmware/linux-firmware-cyw-fmac-utils-imx64_git.bb @@ -29,4 +29,4 @@ FILES:${PN} += "${sbindir}" RDEPENDS:${PN} += " libnl-nf" COMPATIBLE_MACHINE ?= "^$" -COMPATIBLE_MACHINE:portenta-mx8mm = ".*" +COMPATIBLE_MACHINE:portenta-x8 = ".*" diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/PANEL-0001-panel-simple-from-rpi-6.6y.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/PANEL-0001-panel-simple-from-rpi-6.6y.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/PANEL-0001-panel-simple-from-rpi-6.6y.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/PANEL-0001-panel-simple-from-rpi-6.6y.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/PCIE-0001-PCIE_PHY_CMN_REG063.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/PCIE-0001-PCIE_PHY_CMN_REG063.patch new file mode 100644 index 0000000..eb8defe --- /dev/null +++ b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/PCIE-0001-PCIE_PHY_CMN_REG063.patch @@ -0,0 +1,16 @@ +diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +index b5d63657f9f7..2f9647ac02d6 100644 +--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c ++++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +@@ -146,8 +146,9 @@ static int imx8_pcie_phy_power_on(struct phy *phy) + /* Source clock from SoC internal PLL */ + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); +- writel(AUX_PLL_REFCLK_SEL_SYS_PLL, +- imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); ++ printk("Do not set IMX8MM_PCIE_PHY_CMN_REG063 %s %s %d\n", __FILE__, __func__, __LINE__); ++ /*writel(AUX_PLL_REFCLK_SEL_SYS_PLL, ++ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);*/ + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; + writel(val | ANA_AUX_RX_TERM_GND_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch similarity index 100% rename from meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x9/TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch rename to meta-arduino-bsp/recipes-kernel/linux/linux-imx/generic/TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/imx8mp-astrial/defconfig b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/imx8mp-astrial/defconfig new file mode 100644 index 0000000..d14717a --- /dev/null +++ b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/imx8mp-astrial/defconfig @@ -0,0 +1,1145 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PROFILING=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_ARCH_KEEMBAY=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NUMA=y +CONFIG_XEN=y +CONFIG_ARCH_FORCE_MAX_ORDER=13 +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_CT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_CBS=y +CONFIG_NET_SCH_ETF=y +CONFIG_NET_SCH_TAPRIO=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_FLOWER=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_GATE=y +CONFIG_TSN=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_NET_PKTGEN=m +CONFIG_CAN=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_NXPUART=m +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCI_MESON=m +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_IMX_SCMI_BBM_CONTROL=y +CONFIG_IMX_SCMI_MISC_CONTROL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_IMX_SEC_ENCLAVE=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_UACCE=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_MEGARAID_SAS=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_NET_DSA_MSCC_FELIX=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_AMD_XGBE=y +CONFIG_ATL1C=m +CONFIG_BCMGENET=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y +CONFIG_FEC=y +CONFIG_FEC_UIO=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_DPAA2_SWITCH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC4=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_NETC_PRB_IERB=y +CONFIG_FSL_ENETC_QOS=y +CONFIG_FSL_NTMP=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_HNS3=y +CONFIG_HNS3_HCLGE=y +CONFIG_HNS3_ENET=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVMDIO=y +CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_GENERIC=m +CONFIG_AQUANTIA_PHY=y +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_NXP_C45_TJA11XX_PHY=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_M_CAN=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_HOSTAP=y +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_KEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_BBNSM_PWRKEY=y +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_I3C=y +CONFIG_SVC_I3C_MASTER=y +CONFIG_SPI=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_SCMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX93=y +CONFIG_PINCTRL_S32V234=y +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_ADP5585=y +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_MAX77620=y +CONFIG_GPIO_SL28CPLD=m +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_FP9931=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_QORIQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_SL28CPLD_WATCHDOG=m +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_XEN_WDT=y +CONFIG_MFD_ADP5585=y +CONFIG_MFD_BD9571MWV=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_IMX_FLEXIO=y +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_FP9931=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX96752=y +CONFIG_MFD_MAX96752_I2C=y +CONFIG_MFD_MAX96789=y +CONFIG_MFD_MAX96789_I2C=y +CONFIG_MFD_MT6397=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_WCD934X=m +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_BD9571MWV=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_FP9931=y +CONFIG_REGULATOR_MP8859=y +CONFIG_REGULATOR_MT6358=y +CONFIG_REGULATOR_MT6397=y +CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PF0900=y +CONFIG_REGULATOR_PF8X00=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_VIDEO_AMPHION_VPU=y +CONFIG_VIDEO_DWC_MIPI_CSIS=y +CONFIG_VIDEO_IMX8_ISI=y +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_VIDEO_NXP_NEOISP=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_OV5640=y +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_AP1302=y +CONFIG_VIDEO_AP130X=m +CONFIG_VIDEO_MT9M114=y +CONFIG_VIDEO_OS08A20=m +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX8MM_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_RAYDIUM_RM692C9=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_MAX96752_LVDS=y +CONFIG_DRM_MAX96789_DSI=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_IMX95_LDB=y +CONFIG_DRM_IMX95_MIPI_DSI=y +CONFIG_DRM_IMX95_PIXEL_INTERLEAVER=y +CONFIG_DRM_IMX95_PIXEL_LINK=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX93_LDB=y +CONFIG_DRM_IMX_DW_MIPI_DSI=y +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_DCNANO=y +CONFIG_DRM_IMX95_DPU=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_EFI=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_LED=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_ALOOP=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_SND_SOC_IMX_CARD=m +CONFIG_SND_SOC_IMX_PCM512X=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8=m +CONFIG_SND_SOC_SOF_IMX8M=m +CONFIG_SND_SOC_SOF_IMX8ULP=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_CROS_EC_CODEC=m +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WM8524=y +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_RPMSG_WM8960=m +CONFIG_SND_SOC_RPMSG_AK4497=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_HID_MULTITOUCH=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF=m +CONFIG_USB_CONN_GPIO=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_SWITCH_GPIO=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA963X=y +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m +CONFIG_EDAC_SYNOPSYS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF2131=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_CROS_EC=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=m +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_BBNSM=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_RTC_DRV_IMX_SM=y +CONFIG_RTC_DRV_IMX_RPMSG=y +CONFIG_DMADEVICES=y +CONFIG_BCM_SBA_RAID=m +CONFIG_FSL_EDMA=y +CONFIG_FSL_QDMA=m +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V3=y +CONFIG_PL330_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_DW_EDMA=y +CONFIG_DW_EDMA_PCIE=y +CONFIG_FSL_DPAA2_QDMA=m +CONFIG_DMATEST=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_DSP=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_IVSHMEM=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_IVSHMEM=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_IMX8_MEDIA_DEVICE=m +CONFIG_MHDP_HDMIRX=y +CONFIG_MHDP_HDMIRX_CEC=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_ETHOSU=y +CONFIG_NEUTRON=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_CHARDEV=m +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_FSL_SAI=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC5=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_CLK_IMX93=y +CONFIG_CLK_IMX95_BLK_CTL=y +CONFIG_HWSPINLOCK=y +CONFIG_ARM_MHU=y +CONFIG_IMX_MBOX=y +CONFIG_PLATFORM_MHU=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_IMX_DSP_REMOTEPROC=m +CONFIG_IMX_NEUTRON_REMOTEPROC=y +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_SOC_BRCMSTB=y +CONFIG_FSL_DPAA=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_RCPM=y +CONFIG_FSL_QIXIS=y +CONFIG_SOC_TI=y +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_IIO=y +CONFIG_FXLS8962AF_I2C=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IMX8QXP_ADC=y +CONFIG_IMX93_ADC=y +CONFIG_MAX9611=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_FXAS21002C=y +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_SENSORS_ISL29018=y +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MPL3115=y +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_PWM=y +CONFIG_PWM_ADP5585=y +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_PWM_RPCHIP=y +CONFIG_PWM_SL28CPLD=m +CONFIG_SL28CPLD_INTC=y +CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8ULP_SIM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_CADENCE_SALVO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_FSL_IMX9_DPHY_RX=y +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_PHY_FSL_IMX8M_PCIE=y +CONFIG_PHY_FSL_IMX8Q_PCIE=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_ARM_CCI_PMU=m +CONFIG_ARM_CCN=m +CONFIG_ARM_CMN=m +CONFIG_ARM_SMMU_V3_PMU=m +CONFIG_ARM_DSU_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_FSL_IMX9_DDR_PMU=y +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m +CONFIG_HISI_PMU=y +CONFIG_MALI_MIDGARD=y +CONFIG_MALI_CSF_SUPPORT=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_RMEM=m +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_MXC_SIM=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_EMVSIM=y +CONFIG_MXC_VIDEO_WAVE6=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_TRUSTED_KEYS=m +# CONFIG_TRUSTED_KEYS_TPM is not set +# CONFIG_TRUSTED_KEYS_TEE is not set +CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_HISI_SEC2=m +CONFIG_CRYPTO_DEV_HISI_ZIP=m +CONFIG_CRYPTO_DEV_HISI_HPRE=m +CONFIG_CRYPTO_DEV_HISI_TRNG=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC8=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_CATU=m +CONFIG_CORESIGHT_SINK_TPIU=m +CONFIG_CORESIGHT_SINK_ETBV10=m +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_STM=m +CONFIG_CORESIGHT_CPU_DEBUG=m +CONFIG_CORESIGHT_CTI=m +CONFIG_MEMTEST=y diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/DVFS-0001-Add_400MHz_200MHz_100MHz.patch b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/DVFS-0001-Add_400MHz_200MHz_100MHz.patch new file mode 100644 index 0000000..0bf3244 --- /dev/null +++ b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/DVFS-0001-Add_400MHz_200MHz_100MHz.patch @@ -0,0 +1,86 @@ +From c3253354e3eaa04f88a371b30bb6c0751a1f92eb Mon Sep 17 00:00:00 2001 +From: maidnl +Date: Tue, 6 May 2025 14:51:53 +0200 +Subject: [PATCH] added 400MHz 200MHz 100MHz + +--- + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 48 +++++++++++++++++++++++ + drivers/clk/imx/clk-pll14xx.c | 3 ++ + 2 files changed, 51 insertions(+) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +index 6f7a6eee68ef..cffea9baba19 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -156,6 +156,54 @@ a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + ++ opp-100000000 { ++ opp-hz = /bits/ 64 <100000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <850000>; ++ opp-supported-hw = <0xe>, <0x7>; ++ clock-latency-ns = <150000>; ++ opp-suspend; ++ }; ++ + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; +diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c +index 6c17786ecb9f..c4b4ba35376d 100644 +--- a/drivers/clk/imx/clk-pll14xx.c ++++ b/drivers/clk/imx/clk-pll14xx.c +@@ -56,6 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { + PLL_1416X_RATE(700000000U, 350, 3, 2), + PLL_1416X_RATE(640000000U, 320, 3, 2), + PLL_1416X_RATE(600000000U, 300, 3, 2), ++ PLL_1416X_RATE(400000000U, 200, 3, 2), ++ PLL_1416X_RATE(200000000U, 200, 3, 3), ++ PLL_1416X_RATE(100000000U, 200, 3, 4), + PLL_1416X_RATE(320000000U, 160, 3, 2), + }; + +-- +2.43.0 + diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/defconfig b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/defconfig new file mode 100644 index 0000000..84d759a --- /dev/null +++ b/meta-arduino-bsp/recipes-kernel/linux/linux-imx/portenta-x8/defconfig @@ -0,0 +1,1148 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PROFILING=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_ARCH_KEEMBAY=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_S32=y +CONFIG_SOC_S32V234=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NUMA=y +CONFIG_XEN=y +CONFIG_ARCH_FORCE_MAX_ORDER=13 +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_IMX_CPUFREQ_DT=y +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_QORIQ_CPUFREQ=y +CONFIG_ACPI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_TLS=y +CONFIG_TLS_DEVICE=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_CT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_IP_VS=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_CBS=y +CONFIG_NET_SCH_ETF=y +CONFIG_NET_SCH_TAPRIO=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_FLOWER=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_GATE=y +CONFIG_TSN=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_NET_PKTGEN=m +CONFIG_CAN=m +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_NXPUART=m +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_PCIE_ALTERA=y +CONFIG_PCIE_ALTERA_MSI=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_XGENE=y +CONFIG_PCI_MESON=m +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IMX6_EP=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_HISI=y +CONFIG_PCIE_KIRIN=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_FSL_MC_UAPI_SUPPORT=y +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_IMX_SCMI_BBM_CONTROL=y +CONFIG_IMX_SCMI_MISC_CONTROL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_DSP=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +CONFIG_IMX_SEC_ENCLAVE=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_DENALI_DT=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_FSL_IFC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m +CONFIG_XEN_BLKDEV_BACKEND=m +CONFIG_VIRTIO_BLK=y +CONFIG_BLK_DEV_NVME=y +CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=y +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_UACCE=m +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_HISI_SAS_PCI=y +CONFIG_MEGARAID_SAS=y +CONFIG_SCSI_MPT3SAS=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_CEVA=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=y +CONFIG_NET_DSA_MSCC_FELIX=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_AMD_XGBE=y +CONFIG_ATL1C=m +CONFIG_BCMGENET=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_MACB=y +CONFIG_THUNDER_NIC_PF=y +CONFIG_FEC=y +CONFIG_FEC_UIO=y +CONFIG_FSL_FMAN=y +CONFIG_FSL_DPAA_ETH=y +CONFIG_FSL_DPAA2_ETH=y +CONFIG_FSL_DPAA2_MAC=y +CONFIG_FSL_DPAA2_SWITCH=y +CONFIG_FSL_ENETC=y +CONFIG_FSL_ENETC4=y +CONFIG_FSL_ENETC_VF=y +CONFIG_FSL_NETC_PRB_IERB=y +CONFIG_FSL_ENETC_QOS=y +CONFIG_FSL_NTMP=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_HNS3=y +CONFIG_HNS3_HCLGE=y +CONFIG_HNS3_ENET=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_MVMDIO=y +CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MSCC_OCELOT_SWITCH=y +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_GENERIC=m +CONFIG_AQUANTIA_PHY=y +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_NXP_C45_TJA11XX_PHY=y +CONFIG_NXP_TJA11XX_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_M_CAN=m +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_ZAURUS=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_HOSTAP=y +CONFIG_WL18XX=m +CONFIG_WLCORE_SDIO=m +CONFIG_XEN_NETDEV_BACKEND=m +CONFIG_IVSHMEM_NET=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_RPMSG=y +CONFIG_KEYBOARD_SNVS_PWRKEY=y +CONFIG_KEYBOARD_IMX_SC_KEY=y +CONFIG_KEYBOARD_CROS_EC=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_BBNSM_PWRKEY=y +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_LEGACY_PTY_COUNT=16 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_GPIO=m +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_I3C=y +CONFIG_SVC_I3C_MASTER=y +CONFIG_SPI=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_SPI_NXP_FLEXSPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_FSL_DSPI=y +CONFIG_SPI_PL022=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_SCMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX93=y +CONFIG_PINCTRL_S32V234=y +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_IMX_RPMSG=y +CONFIG_GPIO_MB86S7X=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_XGENE=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_ADP5585=y +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_MAX77620=y +CONFIG_GPIO_SL28CPLD=m +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_SBS=m +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_FP9931=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SL28CPLD=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_IMX_SC_THERMAL=y +CONFIG_IMX8MM_THERMAL=y +CONFIG_QORIQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_SL28CPLD_WATCHDOG=m +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_SC_WDT=y +CONFIG_IMX7ULP_WDT=y +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_XEN_WDT=y +CONFIG_MFD_ADP5585=y +CONFIG_MFD_BD9571MWV=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_IMX_FLEXIO=y +CONFIG_MFD_HI6421_PMIC=y +CONFIG_MFD_FP9931=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX96752=y +CONFIG_MFD_MAX96752_I2C=y +CONFIG_MFD_MAX96789=y +CONFIG_MFD_MAX96789_I2C=y +CONFIG_MFD_MT6397=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_ROHM_BD718XX=y +CONFIG_MFD_WCD934X=m +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD718XX=y +CONFIG_REGULATOR_BD9571MWV=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_HI6421V530=y +CONFIG_REGULATOR_MAX77620=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_FP9931=y +CONFIG_REGULATOR_MP8859=y +CONFIG_REGULATOR_MT6358=y +CONFIG_REGULATOR_MT6397=y +CONFIG_REGULATOR_PCA9450=y +CONFIG_REGULATOR_PF0900=y +CONFIG_REGULATOR_PF8X00=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +# CONFIG_DVB_NET is not set +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MX8_CAPTURE=y +CONFIG_VIDEO_MXC_CAPTURE=y +CONFIG_VIDEO_MXC_CSI_CAMERA=y +CONFIG_MXC_MIPI_CSI=y +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y +CONFIG_VIDEO_AMPHION_VPU=y +CONFIG_VIDEO_DWC_MIPI_CSIS=y +CONFIG_VIDEO_IMX8_ISI=y +CONFIG_VIDEO_IMX8_JPEG=m +CONFIG_VIDEO_NXP_NEOISP=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_OV5640=y +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_AP1302=y +CONFIG_VIDEO_AP130X=m +CONFIG_VIDEO_MT9M114=y +CONFIG_VIDEO_OS08A20=m +CONFIG_IMX_DPU_CORE=y +CONFIG_IMX8MM_LCDIF_CORE=y +CONFIG_IMX_LCDIFV3_CORE=y +CONFIG_DRM=y +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_MALI_DISPLAY=m +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_RAYDIUM_RM692C9=y +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_WKS_101WX001=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y +CONFIG_DRM_MAX96752_LVDS=y +CONFIG_DRM_MAX96789_DSI=y +CONFIG_DRM_NWL_MIPI_DSI=y +CONFIG_DRM_NXP_SEIKO_43WVFIG=y +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_I2C_ADV7511=y +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_IMX95_LDB=y +CONFIG_DRM_IMX95_MIPI_DSI=y +CONFIG_DRM_IMX95_PIXEL_INTERLEAVER=y +CONFIG_DRM_IMX95_PIXEL_LINK=y +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_GP_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_ITE_IT6263=y +CONFIG_DRM_ITE_IT6161=y +CONFIG_DRM_IMX=y +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y +CONFIG_DRM_IMX_TVE=y +CONFIG_DRM_IMX_LDB=y +CONFIG_DRM_IMX8QM_LDB=y +CONFIG_DRM_IMX8QXP_LDB=y +CONFIG_DRM_IMX8MP_LDB=y +CONFIG_DRM_IMX93_LDB=y +CONFIG_DRM_IMX_DW_MIPI_DSI=y +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y +CONFIG_DRM_IMX_HDMI=y +CONFIG_DRM_IMX_SEC_DSIM=y +CONFIG_DRM_IMX_DCNANO=y +CONFIG_DRM_IMX95_DPU=y +CONFIG_DRM_IMX_DCSS=y +CONFIG_DRM_IMX_CDNS_MHDP=y +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_HISI_HIBMC=m +CONFIG_DRM_HISI_KIRIN=m +CONFIG_DRM_MXSFB=y +CONFIG_DRM_PL111=m +CONFIG_DRM_LIMA=m +CONFIG_DRM_PANFROST=m +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_EFI=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_LED=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_ALOOP=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SGTL5000=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m +CONFIG_SND_SOC_IMX_HDMI=m +CONFIG_SND_SOC_IMX_CARD=m +CONFIG_SND_SOC_IMX_PCM512X=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y +CONFIG_SND_SOC_SOF_IMX8=m +CONFIG_SND_SOC_SOF_IMX8M=m +CONFIG_SND_SOC_SOF_IMX8ULP=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_BT_SCO=y +CONFIG_SND_SOC_CROS_EC_CODEC=m +CONFIG_SND_SOC_CS42XX8_I2C=y +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WM8524=y +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_RPMSG_WM8960=m +CONFIG_SND_SOC_RPMSG_AK4497=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_HID_MULTITOUCH=m +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF=m +CONFIG_USB_CONN_GPIO=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=y +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_SWITCH_GPIO=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA963X=y +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_EDAC=y +CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m +CONFIG_EDAC_SYNOPSYS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF2131=m +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_CROS_EC=y +CONFIG_RTC_DRV_FSL_FTM_ALARM=m +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_BBNSM=y +CONFIG_RTC_DRV_IMX_SC=y +CONFIG_RTC_DRV_IMX_SM=y +CONFIG_RTC_DRV_IMX_RPMSG=y +CONFIG_DMADEVICES=y +CONFIG_BCM_SBA_RAID=m +CONFIG_FSL_EDMA=y +CONFIG_FSL_QDMA=m +CONFIG_FSL_EDMA_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MV_XOR_V2=y +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V3=y +CONFIG_PL330_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_DW_EDMA=y +CONFIG_DW_EDMA_PCIE=y +CONFIG_FSL_DPAA2_QDMA=m +CONFIG_DMATEST=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_DSP=y +CONFIG_UIO_PCI_GENERIC=y +CONFIG_UIO_IVSHMEM=y +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_IVSHMEM=y +CONFIG_XEN_GNTDEV=y +CONFIG_XEN_GRANT_DEV_ALLOC=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_IMX_CAPTURE=y +CONFIG_IMX8_MEDIA_DEVICE=m +CONFIG_MHDP_HDMIRX=y +CONFIG_MHDP_HDMIRX_CEC=y +CONFIG_FSL_DPAA2=y +CONFIG_FSL_PPFE=y +CONFIG_FSL_PPFE_UTIL_DISABLED=y +CONFIG_ETHOSU=y +CONFIG_NEUTRON=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_CHARDEV=m +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_CS2000_CP=y +CONFIG_COMMON_CLK_FSL_SAI=y +CONFIG_COMMON_CLK_S2MPS11=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC5=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_CLK_IMX93=y +CONFIG_CLK_IMX95_BLK_CTL=y +CONFIG_HWSPINLOCK=y +CONFIG_ARM_MHU=y +CONFIG_IMX_MBOX=y +CONFIG_PLATFORM_MHU=y +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_REMOTEPROC=y +CONFIG_IMX_REMOTEPROC=y +CONFIG_IMX_DSP_REMOTEPROC=m +CONFIG_IMX_NEUTRON_REMOTEPROC=y +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_SOC_BRCMSTB=y +CONFIG_FSL_DPAA=y +CONFIG_FSL_MC_DPIO=y +CONFIG_FSL_RCPM=y +CONFIG_FSL_QIXIS=y +CONFIG_SOC_TI=y +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_IIO=y +CONFIG_FXLS8962AF_I2C=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IMX8QXP_ADC=y +CONFIG_IMX93_ADC=y +CONFIG_MAX9611=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_FXAS21002C=y +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_FXOS8700_I2C=y +CONFIG_RPMSG_IIO_PEDOMETER=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_IIO_ST_LSM6DSX=y +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +CONFIG_SENSORS_ISL29018=y +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_CROS_EC_BARO=m +CONFIG_MPL3115=y +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_PWM=y +CONFIG_PWM_ADP5585=y +CONFIG_PWM_CROS_EC=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_IMX27=y +CONFIG_PWM_IMX_TPM=y +CONFIG_PWM_RPCHIP=y +CONFIG_PWM_SL28CPLD=m +CONFIG_SL28CPLD_INTC=y +CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8ULP_SIM=y +CONFIG_PHY_MIXEL_LVDS=y +CONFIG_PHY_MIXEL_LVDS_COMBO=y +CONFIG_PHY_CADENCE_SALVO=y +CONFIG_PHY_FSL_IMX8MP_LVDS=y +CONFIG_PHY_FSL_IMX9_DPHY_RX=y +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y +CONFIG_PHY_MIXEL_MIPI_DPHY=y +CONFIG_PHY_FSL_IMX8M_PCIE=y +CONFIG_PHY_FSL_IMX8Q_PCIE=y +CONFIG_PHY_SAMSUNG_HDMI_PHY=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_ARM_CCI_PMU=m +CONFIG_ARM_CCN=m +CONFIG_ARM_CMN=m +CONFIG_ARM_SMMU_V3_PMU=m +CONFIG_ARM_DSU_PMU=m +CONFIG_FSL_IMX8_DDR_PMU=y +CONFIG_FSL_IMX9_DDR_PMU=y +CONFIG_ARM_SPE_PMU=m +CONFIG_ARM_DMC620_PMU=m +CONFIG_HISI_PMU=y +CONFIG_MALI_MIDGARD=y +CONFIG_MALI_CSF_SUPPORT=y +CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_IMX_OCOTP_SCU=y +CONFIG_NVMEM_RMEM=m +CONFIG_FPGA=y +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_MXC_SIM=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_EMVSIM=y +CONFIG_MXC_VIDEO_WAVE6=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_TRUSTED_KEYS=m +# CONFIG_TRUSTED_KEYS_TPM is not set +# CONFIG_TRUSTED_KEYS_TEE is not set +CONFIG_SECURITY=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_TLS=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_HISI_SEC2=m +CONFIG_CRYPTO_DEV_HISI_ZIP=m +CONFIG_CRYPTO_DEV_HISI_HPRE=m +CONFIG_CRYPTO_DEV_HISI_TRNG=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +CONFIG_INDIRECT_PIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC8=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_CATU=m +CONFIG_CORESIGHT_SINK_TPIU=m +CONFIG_CORESIGHT_SINK_ETBV10=m +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_STM=m +CONFIG_CORESIGHT_CPU_DEBUG=m +CONFIG_CORESIGHT_CTI=m +CONFIG_MEMTEST=y diff --git a/meta-arduino-bsp/recipes-kernel/linux/linux-imx_%.bbappend b/meta-arduino-bsp/recipes-kernel/linux/linux-imx_%.bbappend index 7739dcb..8981c0e 100644 --- a/meta-arduino-bsp/recipes-kernel/linux/linux-imx_%.bbappend +++ b/meta-arduino-bsp/recipes-kernel/linux/linux-imx_%.bbappend @@ -1,21 +1,34 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" +SRC_URI:append = " \ + file://generic/PCIE-0001-PCIE_PHY_CMN_REG063.patch \ + file://generic/EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch \ + file://generic/EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch \ + file://generic/EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch \ + file://generic/EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch \ + file://generic/EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch \ + file://generic/EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch \ + file://generic/PANEL-0001-panel-simple-from-rpi-6.6y.patch \ + file://generic/ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch \ + file://generic/ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch \ + file://generic/ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch \ + file://generic/TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch \ + file://generic/TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch \ + file://generic/TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch \ + file://generic/ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch \ +" + +SRC_URI:append:portenta-x8 = " \ + file://defconfig \ + file://DVFS-0001-Add_400MHz_200MHz_100MHz.patch \ +" + SRC_URI:append:portenta-x9 = " \ file://defconfig \ - file://EDT-0001-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch \ - file://EDT-0002-Input-edt-ft54x6-Clean-up-timer-and-workqueue-on-rem.patch \ - file://EDT-0003-input-touchscreen-edt-ft5x06-Suppress-bogus-data-on-.patch \ - file://EDT-0004-input-edt-ft5x06-Include-I2C-details-in-names-for-th.patch \ - file://EDT-0005-input-edt-ft5x06-Correct-prefix-length-in-snprintf.patch \ - file://EDT-0006-Input-edt-ft5x06-fix-regmap-leak-when-probe-fails.patch \ - file://PANEL-0001-panel-simple-from-rpi-6.6y.patch \ - file://ATTINY-0001-regulator-rpi-panel-attiny-Don-t-read-the-LCD-power-.patch \ - file://ATTINY-0002-regulator-rpi-panel-Power-off-display-on-shutdown.patch \ - file://ATTINY-0003-regulator-rpi-panel-Remove-the-ID-read.patch \ - file://TOSHIBA-0001-drm-bridge-tc358762-Ignore-EPROBE_DEFER-when-logging.patch \ - file://TOSHIBA-0002-drm-bridge-tc358762-Program-the-DPI-mode-into-the-ch.patch \ - file://TOSHIBA-0003-drm-bridge-tc358762-revert-move-ops-to-enable.patch \ - file://ISI-0001-Added-support-for-RAW-bayer-formats-on-imx8-platform.patch \ +" + +SRC_URI:append:imx8mp-astrial = " \ + file://defconfig \ " # This is because methods in meta-imx-bsp/recipes-kernel/linux/linux-imx_6.6.bb diff --git a/meta-arduino-bsp/recipes-support/images/arduino-image.inc b/meta-arduino-bsp/recipes-support/images/arduino-image.inc index bd45dd6..0027c30 100644 --- a/meta-arduino-bsp/recipes-support/images/arduino-image.inc +++ b/meta-arduino-bsp/recipes-support/images/arduino-image.inc @@ -1,17 +1,6 @@ # Setup image features IMAGE_FEATURES:append = " ssh-server-dropbear" -# Following packages are already included in -# MACHINE_EXTRA_RRECOMMENDS -CORE_IMAGE_EXTRA_INSTALL:append:portenta-x9 = " arduino-device-tree" -CORE_IMAGE_EXTRA_INSTALL:append:portenta-x9 = " \ - kernel-module-nxp-wlan \ - firmware-nxp-wifi-nxpiw612-sdio \ - firmware-nxp-wifi \ - kernel-module-btnxpuart \ - lmbench \ -" - # Install extra out of tree kernel drivers (som) CORE_IMAGE_EXTRA_INSTALL += " \ dtbocfg \ @@ -58,6 +47,8 @@ CORE_IMAGE_EXTRA_INSTALL += " \ CORE_IMAGE_EXTRA_INSTALL += " \ packagegroup-base \ systemd \ + networkmanager \ + networkmanager-wifi \ networkmanager-nmcli \ iperf3 \ openocd \ @@ -117,3 +108,11 @@ write_git_sha() { } ROOTFS_POSTPROCESS_COMMAND += "write_git_sha; " + +# Late rootfs tweaks +late_rootfs_tweaks() { + # Remove interfaces from init-ifupdown + rm ${IMAGE_ROOTFS}/etc/network/interfaces +} + +ROOTFS_POSTPROCESS_COMMAND += "late_rootfs_tweaks; " \ No newline at end of file