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Commits on Aug 21, 2020

• Add RegFile parameter for selecting register file implementation

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• [rtl] Fix FENCE comment in decoder

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  Tom Roberts

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• Add private CI trigger

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• CI: Factor out installation of build dependencies

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• CI: Script to convert CI variables

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• Add lowRISC-specific version of Spike to CI config

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• Factor out CI variables into separate file

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Commits on Aug 20, 2020

• Fix PRJ_DIR in DV Makefile

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• Update google_riscv-dv to chipsalliance/riscv-dv@2e52518

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• Doc support for overriding enum/string parameters at the top level

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• Add a single RV32M enum parameter to select multiplier implementation

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• B extension: Correct doc and parameter usage

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• Use a RV32IMCB toolchain in CI

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Commits on Aug 17, 2020

• [ibex/dv] Add dependency on bus_params_pkg

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• Update google_riscv-dv to chipsalliance/riscv-dv@17d7984

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• Update lowrisc_ip to lowRISC/opentitan@92e92424

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Commits on Aug 11, 2020

• [ibex/dv] Update OVPsim to use 34-bit address range

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• [rtl] remove lsu_req_in_id signal

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• [doc] Fix table rendering in README

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Commits on Aug 10, 2020

• [ibex/ml] Update the ML testlist

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• [ibex] Update CSR description of cpuctrl/secureseed

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• [syn] Use latch-based register file in yosys

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  Tom Roberts

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Commits on Aug 6, 2020

• [ibex/dv] Update Ibex PMP tests

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Commits on Aug 5, 2020

• Update google_riscv-dv to chipsalliance/riscv-dv@61755c0

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• [ibex/rtl] Fix pmpaddr write enable signal

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Commits on Aug 4, 2020

• Set FPGA_XILINX define whenever Vivado is used

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Commits on Aug 3, 2020

• [doc] Update FPGA Synthesis Paragraph in Intro

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Commits on Jul 30, 2020

• Fix typo in examples/sw/benchmarks/README.md

  

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• Add myself to CREDITS.md

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• Remove Verible lint workaround

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Commits on Jul 24, 2020

• [dv] Add custom CSRs to yaml description file

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• [dv/ibex] Update CSR listings

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• Update google_riscv-dv to chipsalliance/riscv-dv@3cf691d

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• Properly vendor in mem_model from OpenTitan

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• Update lowrisc_ip to lowRISC/opentitan@067272a2

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