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Starred repositories

5 stars written in SystemVerilog
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A Framework for Design and Verification of Image Processing Applications using UVM

SystemVerilog 92 38 Updated Nov 27, 2017

A simple UVM example with DPI

SystemVerilog 38 17 Updated Aug 7, 2017

Implements a simple UVM based testbench for a simple memory DUT.

SystemVerilog 12 20 Updated Oct 26, 2019

A simple UVM testbench using UVM Connect and Octave

SystemVerilog 9 1 Updated Aug 7, 2017

UVM VIP for Single Port RAM Synchronous Read/Write

SystemVerilog 5 1 Updated Jul 15, 2020