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Commits on Dec 23, 2024

• riscv: asm: amend documents to mention Xuantie C908 core supported assembly functions

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Commits on Dec 15, 2024

• riscv: asm: amend documents to mention Xuantie C907 core supported assembly functions

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• riscv: emit risc-v instruction assembly only on riscv32 and riscv64 target_arch configurations

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Commits on Dec 14, 2024

• fix: plic: detect priority and threshold bits in any cases

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• riscv: add Xuantie PLIC peripheral support

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• bump: downgrade cargo edition to 2021 (rustsbi#5)

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Commits on Dec 12, 2024

• riscv: enable smel register only on 64-bit xuantie cores

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• riscv: implement Entry and Flags only when target_pointer_width = "64"

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• ci: update rust check workflow to assume MSRV at rustc nightly-2024-12-11

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• Set up GitHub CI for rustsbi/xuantie with formatting and RISC-V checks (rustsbi#4)

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• rt: add interrupt dispatcher symbol

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• refactor: rename xuantie crate to xuantie-riscv crate (rustsbi#3)

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• asm: improve internal modular design of T-Head instruction sets

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Commits on Dec 11, 2024

• docs: add periods to sentences, amend documents on clint registers

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• feat: Added T-Head clint driver (rustsbi#2)

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Commits on Oct 15, 2022

• asm: add dsp proposal v0.9 extension

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Commits on Oct 10, 2022

• fix: default target to riscv64imac-unknown-none-elf

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Commits on Aug 2, 2022

• Move repository to rustsbi/xuantie

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• small fix

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Commits on Apr 20, 2022

• crate: update version to 0.0.5

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• doc: remove unverified example

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Commits on Apr 19, 2022

• asm: spell check on documents

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• cpuid: rename fetch function to read

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Commits on Apr 18, 2022

• crate: announce 0.0.4 version

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• csr: update mcpuid register

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• doc: enable and invalidate caches

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• lib: add some examples

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• announce 0.0.3 version

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• asm: small fix on dcache.cpa

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• asm, register: e907 features

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• asm, register: add e906 core features

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• asm, register: amend e902 instructions and CSRs

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• asm: c910 cache sync instruction

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• asm: c910 l2 cache instructions

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• crate: update edition to 2021

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