add wrapper to generate verilog

Author: sashimi-yzh

.gitignore

@@ -4,3 +4,5 @@ out/
 .idea/
 .idea_modules/
 test_run_dir/
+
+build/

Makefile

@@ -1,3 +1,15 @@
+BUILD_DIR = ./build
+
+test:
+	mill -i __.test
+
+verilog:
+	mkdir -p $(BUILD_DIR)
+	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
+
+help:
+	mill -i __.test.runMain Elaborate --help
+
 compile:
 	mill -i __.compile
 
@@ -14,7 +26,6 @@ reformat:
 	mill -i __.reformat
 
 checkformat:
-	mill -i __.checkFormat 
+	mill -i __.checkFormat
 
-test:
-	mill -i __.test
+.PHONY: test verilog help compile bsp reformat checkformat clean

playground/src/Elaborate.scala

@@ -0,0 +1,3 @@
+object Elaborate extends App {
+  (new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new GCD())))
+}