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base repository: OSCPU/chisel-playground
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base: master
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head repository: OSCPU/chisel-playground
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compare: chisel-SInt
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  • 9 commits
  • 12 files changed
  • 2 contributors

Commits on Oct 3, 2022

  1. add support for MLIR-based firrtl compiler

    @sashimi-yzh
    sashimi-yzh committed Oct 3, 2022
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Commits on Oct 10, 2022

  1. trace code

    @sashimi-yzh
    sashimi-yzh committed Oct 10, 2022
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Commits on Apr 3, 2023

  1. Makefile: ignore error for include

    @sashimi-yzh
    sashimi-yzh committed Apr 3, 2023
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Commits on Jun 17, 2023

  1. build.sc: use faster mirror

    @sashimi-yzh
    sashimi-yzh committed Jun 17, 2023
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Commits on Jun 22, 2023

  1. utils,firtool: generate verilog for verilator and yosys 

    * see https://github.com/llvm/circt/blob/main/docs/VerilogGeneration.md
    @sashimi-yzh
    sashimi-yzh committed Jun 22, 2023
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Commits on Jul 2, 2023

  1. bump chisel to 5.0.0

    @sashimi-yzh
    sashimi-yzh committed Jul 2, 2023
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Commits on Nov 10, 2023

  1. build.sc: fix compile error with latest mill

    @sashimi-yzh
    sashimi-yzh committed Nov 10, 2023
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Commits on Jan 15, 2024

  1. Bump 6.0.0-RC2 and Mill

    @poemonsense
    poemonsense committed Jan 15, 2024
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  2. Update testcase for SInt

    @poemonsense
    poemonsense committed Jan 15, 2024
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