From 5fee746fd0302ec359ab91f479e35f379b707942 Mon Sep 17 00:00:00 2001 From: linzhida Date: Mon, 13 Jan 2025 13:21:47 +0800 Subject: [PATCH 1/4] fix(aia): add the missing AIA-related permission checks Along the same lines, when hstatus.VGEIN is not the number of an implemented guest external interrupt, attempts from M-mode or HS-mode to access CSR vstopei raise an illegal instruction exception, and attempts from VS-mode to access stopei raise a virtual instruction exception. --- .../xiangshan/backend/fu/NewCSR/CSRAIA.scala | 2 +- .../backend/fu/NewCSR/CSRPermitModule.scala | 18 ++++++++++++++---- .../backend/fu/NewCSR/HypervisorLevel.scala | 4 +--- .../xiangshan/backend/fu/NewCSR/NewCSR.scala | 4 +++- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala index a2640480140..0f679129170 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala @@ -236,7 +236,7 @@ class CSRToAIABundle extends Bundle { } class AIAToCSRBundle extends Bundle { - private val NumVSIRFiles = 63 + private val NumVSIRFiles = 5 val rdata = ValidIO(new Bundle { val data = UInt(XLEN.W) val illegal = Bool() diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala index 85e6bc06a30..31c744c74b5 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala @@ -65,15 +65,16 @@ class CSRPermitModule extends Module { val pPermit_EX_II = privilegePermitMod.io.out.privilege_EX_II val pPermit_EX_VI = privilegePermitMod.io.out.privilege_EX_VI + val vPermit_EX_II = virtualLevelPermitMod.io.out.virtualLevelPermit_EX_II val vPermit_EX_VI = virtualLevelPermitMod.io.out.virtualLevelPermit_EX_VI val indirectPermit_EX_II = indirectCSRPermitMod.io.out.indirectCSR_EX_II val indirectPermit_EX_VI = indirectCSRPermitMod.io.out.indirectCSR_EX_VI - val directPermit_illegal = mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || pPermit_EX_VI || vPermit_EX_VI + val directPermit_illegal = mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || pPermit_EX_VI || vPermit_EX_II || vPermit_EX_VI val csrAccess_EX_II = csrAccess && ( - (mPermit_EX_II || sPermit_EX_II || pPermit_EX_II) || + (mPermit_EX_II || sPermit_EX_II || pPermit_EX_II || vPermit_EX_II) || (!directPermit_illegal && indirectPermit_EX_II) ) val csrAccess_EX_VI = csrAccess && ( @@ -380,6 +381,7 @@ class VirtualLevelPermitModule extends Module { val aia = new aiaIO }) val out = Output(new Bundle { + val virtualLevelPermit_EX_II = Bool() val virtualLevelPermit_EX_VI = Bool() }) }) @@ -390,7 +392,10 @@ class VirtualLevelPermitModule extends Module { io.in.privState, ) - private val vtvm = io.in.status.vtvm + private val (vtvm, vgein) = ( + io.in.status.vtvm, + io.in.status.vgein, + ) private val (hcounteren, scounteren) = ( io.in.xcounteren.hcounteren, @@ -415,6 +420,9 @@ class VirtualLevelPermitModule extends Module { private val rwSatp_EX_VI = privState.isModeVS && vtvm && (addr === CSRs.satp.U) + private val rwVStopei_EX_II = (privState.isModeM || privState.isModeHS) && (addr === CSRs.vstopei.U) && (vgein === 0.U || vgein > CSRConfig.GEILEN.U) + private val rwStopei_EX_VI = privState.isModeVS && (addr === CSRs.stopei.U) && (vgein === 0.U || vgein > CSRConfig.GEILEN.U) + private val rwSip_Sie_EX_VI = privState.isModeVS && hvictlVTI && (addr === CSRs.sip.U || addr === CSRs.sie.U) private val rwStimecmp_EX_VI = privState.isModeVS && (addr === CSRs.stimecmp.U) && @@ -466,7 +474,8 @@ class VirtualLevelPermitModule extends Module { private val xstateControlAccess_EX_VI = accessStateen0_EX_VI || accessEnvcfg_EX_VI || accessIND_EX_VI || accessAIA_EX_VI || accessTopie_EX_VI || accessContext_EX_VI || accessCustom_EX_VI - io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI || accessHPM_EX_VI || xstateControlAccess_EX_VI + io.out.virtualLevelPermit_EX_II := rwVStopei_EX_II + io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwStopei_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI || accessHPM_EX_VI || xstateControlAccess_EX_VI } class IndirectCSRPermitModule extends Module { @@ -538,6 +547,7 @@ class statusIO extends Bundle { val tvm = Bool() // Virtual Trap Virtual Memory val vtvm = Bool() + val vgein = UInt(6.W) val mstatusFSOff = Bool() val vsstatusFSOff = Bool() val mstatusVSOff = Bool() diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala index 0ade0e8fd56..75badb62ad8 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala @@ -219,9 +219,7 @@ class HstatusBundle extends CSRBundle { } -object HstatusVgeinField extends CSREnum with WLRLApply { - override def isLegal(enumeration: CSREnumType): Bool = enumeration.asUInt <= GEILEN.U -} +object HstatusVgeinField extends CSREnum with WLRLApply class HstatusModule(implicit p: Parameters) extends CSRModule("Hstatus", new HstatusBundle) with SretEventSinkBundle diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index 832038603ea..8f92ec34529 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -25,7 +25,7 @@ import xiangshan.backend.trace._ import scala.collection.immutable.SeqMap object CSRConfig { - final val GEILEN = 63 + final val GEILEN = 5 // m,s,5vs final val ASIDLEN = 16 // the length of ASID of XS implementation @@ -469,6 +469,8 @@ class NewCSR(implicit val p: Parameters) extends Module permitMod.io.in.status.tvm := mstatus.regOut.TVM.asBool permitMod.io.in.status.vtvm := hstatus.regOut.VTVM.asBool + permitMod.io.in.status.vgein := hstatus.regOut.VGEIN.asUInt + permitMod.io.in.xcounteren.mcounteren := mcounteren.rdata permitMod.io.in.xcounteren.hcounteren := hcounteren.rdata permitMod.io.in.xcounteren.scounteren := scounteren.rdata From f92761ecf54a5b8a9a24db3cb46d130dfc47d9ee Mon Sep 17 00:00:00 2001 From: linzhida Date: Tue, 14 Jan 2025 13:20:59 +0800 Subject: [PATCH 2/4] feat(difftest): sync hgeip by difftest --- .../scala/xiangshan/backend/fu/NewCSR/NewCSR.scala | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index 8f92ec34529..5b02561ccdb 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -1554,12 +1554,13 @@ class NewCSR(implicit val p: Parameters) extends Module }).orR diffMhpmeventOverflowEvent.mhpmeventOverflow := VecInit(mhpmevents.map(_.regOut.asInstanceOf[MhpmeventBundle].OF.asBool)).asUInt - val diffAIAXtopeiEvent = DifftestModule(new DiffAIAXtopeiEvent) - diffAIAXtopeiEvent.coreid := hartId - diffAIAXtopeiEvent.valid := fromAIA.rdata.valid - diffAIAXtopeiEvent.mtopei := mtopei.rdata - diffAIAXtopeiEvent.stopei := stopei.rdata - diffAIAXtopeiEvent.vstopei := vstopei.rdata + val diffSyncAIAEvent = DifftestModule(new DiffSyncAIAEvent) + diffSyncAIAEvent.coreid := hartId + diffSyncAIAEvent.valid := fromAIA.rdata.valid + diffSyncAIAEvent.mtopei := mtopei.rdata + diffSyncAIAEvent.stopei := stopei.rdata + diffSyncAIAEvent.vstopei := vstopei.rdata + diffSyncAIAEvent.hgeip := hgeip.rdata val diffCustomMflushpwr = DifftestModule(new DiffSyncCustomMflushpwrEvent) diffCustomMflushpwr.coreid := hartId From cde74084744050ac059987cb1fd8b3a495387451 Mon Sep 17 00:00:00 2001 From: linzhida Date: Thu, 16 Jan 2025 18:29:10 +0800 Subject: [PATCH 3/4] submodule(difftest): bump difftest to support sync AIA --- difftest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/difftest b/difftest index 7c070eee8d7..07d1b3e4528 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 7c070eee8d73c0f47d8c814a51701291ad8ee419 +Subproject commit 07d1b3e45287a5c332f3ddd8bf992424f30f8f91 From 13166cadc447c787a9c6dbee68e8e7a91a3edeb2 Mon Sep 17 00:00:00 2001 From: linzhida Date: Thu, 16 Jan 2025 18:30:58 +0800 Subject: [PATCH 4/4] submodule(ready-to-run): Bump nemu ref in ready-to-run * NEMU commit:68c3db24b9a997e847e65893089a608e286c74e3 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig * riscv64-xs-ref-debug_defconfig * riscv64-dual-xs-ref-debug_defconfig Including: * opt(mmu): add an early out fast path (#748) * refactor(makefile): cleanup (#750) * fix(help): fix the help of flash-image parameter (#764) * fix(zvfh): fix zvfh corner case which should support vsew8 (#763) * fix: allow flash use 512M space (#761) * fix: replace local riscv64-nutshell-spike-so with ready-to-run (#760) * feat(difftest): support using difftest override ref flash (#758) * refactor(Makefile): Migrate other repos build logic to separate makefiles (#766) * try-fix(difftest attach): Add 'pmp' and 'pmp_cpy' API to difftest_attach, but functionality remains incomplete (#757) * fix(vaddr): vaddr_read_safe should not check hlvx instruction (#769) * fix: fix init_difftest wrong definition (#772) * fix: split LibcheckpointAlpha build process from menuconfig (#771) * fix(csr, exception): check exception for indirect csr finally * feat(custom): add two M level custom CSR, mcorepwr and mflushpwr * feat(difftest): sync custom CSR mflushpwr.l2flushed by difftest * fix(vslide): fix the decoding of the vslide instruction. * feat(debug): make log output simpler * feat(log): improve inst trace log format * feat: add --store-cpt-in-flash option (#778) * refactor: wrap function definition with #ifdef (#779) * feat: replace fixed get_pmem with serialize_base_addr for checkpoint storage (#780) * feat: support --store-cpt-in-flash option to set serialize_reg_base_addr to flash address (#782) * fix(aia, exception): Add the missing AIA-related permission checks. (#776) * configs(gem5-ref): update gem5 ref config (#784) --- ready-to-run | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ready-to-run b/ready-to-run index 98f779c9140..7b4e611a04e 160000 --- a/ready-to-run +++ b/ready-to-run @@ -1 +1 @@ -Subproject commit 98f779c914017c6fcf173a81c492a77aa9692dbb +Subproject commit 7b4e611a04e7e226039ff8b3087d00c1aed8bb11