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DSi.cpp
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DSi.cpp
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/*
Copyright 2016-2024 melonDS team
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#include <stdio.h>
#include <assert.h>
#include <string.h>
#include <inttypes.h>
#include "Args.h"
#include "NDS.h"
#include "DSi.h"
#include "ARM.h"
#include "GPU.h"
#include "NDSCart.h"
#include "SPI.h"
#include "DSi_SPI_TSC.h"
#include "Platform.h"
#include "ARMJIT.h"
#include "ARMJIT_Memory.h"
#include "DSi_NDMA.h"
#include "DSi_I2C.h"
#include "DSi_SD.h"
#include "DSi_AES.h"
#include "DSi_NAND.h"
#include "DSi_DSP.h"
#include "DSi_Camera.h"
#include "tiny-AES-c/aes.hpp"
namespace melonDS
{
using namespace Platform;
// matching NDMA modes for DSi
const u32 NDMAModes[] =
{
// ARM9
0x10, // immediate
0x06, // VBlank
0x07, // HBlank
0x08, // scanline start
0x09, // mainmem FIFO
0x04, // DS cart slot
0xFF, // GBA cart slot
0x0A, // GX FIFO
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
// ARM7
0x30, // immediate
0x26, // VBlank
0x24, // DS cart slot
0xFF, // wifi / GBA cart slot (TODO)
};
/*DSi::DSi() noexcept :
DSi(
DSiArgs {
NDSArgs {
nullptr,
nullptr,
bios_arm9_bin,
bios_arm7_bin,
Firmware(0),
},
nullptr,
nullptr,
nullptr,
nullptr,
false
}
)
{
}*/
DSi::DSi(DSiArgs&& args, void* userdata) noexcept :
NDS(std::move(args), 1, userdata),
NDMAs {
DSi_NDMA(0, 0, *this),
DSi_NDMA(0, 1, *this),
DSi_NDMA(0, 2, *this),
DSi_NDMA(0, 3, *this),
DSi_NDMA(1, 0, *this),
DSi_NDMA(1, 1, *this),
DSi_NDMA(1, 2, *this),
DSi_NDMA(1, 3, *this),
},
ARM7iBIOS(*args.ARM7iBIOS),
ARM9iBIOS(*args.ARM9iBIOS),
DSP(*this),
SDMMC(*this, std::move(args.NANDImage), std::move(args.DSiSDCard)),
SDIO(*this),
I2C(*this),
CamModule(*this),
AES(*this)
{
// Memory is owned by ARMJIT_Memory, don't free it
NWRAM_A = JIT.Memory.GetNWRAM_A();
NWRAM_B = JIT.Memory.GetNWRAM_B();
NWRAM_C = JIT.Memory.GetNWRAM_C();
}
DSi::~DSi() noexcept
{
// Memory is owned externally
NWRAM_A = nullptr;
NWRAM_B = nullptr;
NWRAM_C = nullptr;
}
void DSi::Reset()
{
//ARM9.CP15Write(0x910, 0x0D00000A);
//ARM9.CP15Write(0x911, 0x00000020);
//ARM9.CP15Write(0x100, ARM9.CP15Read(0x100) | 0x00050000);
NDS::Reset();
// The SOUNDBIAS register does nothing on DSi
SPU.SetApplyBias(false);
KeyInput &= ~(1 << (16+6));
MapSharedWRAM(3);
NDMACnt[0] = 0; NDMACnt[1] = 0;
for (int i = 0; i < 8; i++) NDMAs[i].Reset();
I2C.Reset();
CamModule.Reset();
DSP.Reset();
LoadNAND();
SDMMC.Reset();
SDIO.Reset();
AES.Reset();
if (FullBIOSBoot)
{
SCFG_BIOS = 0x0000;
}
else
{
SCFG_BIOS = 0x0101;
}
SCFG_Clock9 = 0x0187; // CHECKME
SCFG_Clock7 = 0x0187;
SCFG_EXT[0] = 0x8307F100;
SCFG_EXT[1] = 0x93FFFB06;
SCFG_MC = 0x0010 | (~((u32)(NDSCartSlot.GetCart() != nullptr))&1);//0x0011;
SCFG_RST = 0;
DSP.SetRstLine(false);
GPIO_Data = 0xff; // these actually initialize to high after reset
GPIO_Dir = 0x80; // enable sound out, all others input
GPIO_IEdgeSel = 0;
GPIO_IE = 0;
GPIO_WiFi = 0;
// LCD init flag
GPU.DispStat[0] |= (1<<6);
GPU.DispStat[1] |= (1<<6);
}
void DSi::Stop(Platform::StopReason reason)
{
NDS::Stop(reason);
CamModule.Stop();
}
void DSi::SetNDSCart(std::unique_ptr<NDSCart::CartCommon>&& cart)
{
NDS::SetNDSCart(std::move(cart));
SetCartInserted(NDSCartSlot.GetCart() != nullptr);
}
std::unique_ptr<NDSCart::CartCommon> DSi::EjectCart()
{
auto oldcart = NDS::EjectCart();
SetCartInserted(false);
return oldcart;
}
void DSi::CamInputFrame(int cam, const u32* data, int width, int height, bool rgb)
{
switch (cam)
{
case 0: return I2C.GetOuterCamera()->InputFrame(data, width, height, rgb);
case 1: return I2C.GetInnerCamera()->InputFrame(data, width, height, rgb);
}
}
void DSi::DoSavestateExtra(Savestate* file)
{
file->Section("DSIG");
file->Var16(&SCFG_BIOS);
file->Var16(&SCFG_Clock9);
file->Var16(&SCFG_Clock7);
file->VarArray(&SCFG_EXT[0], sizeof(u32)*2);
file->Var32(&SCFG_MC);
file->Var16(&SCFG_RST);
//file->VarArray(ARM9iBIOS, 0x10000);
//file->VarArray(ARM7iBIOS, 0x10000);
if (file->Saving)
{
file->VarArray(&MBK[0][0], sizeof(u32)*8);
file->VarArray(&MBK[1][5], sizeof(u32)*3);
file->Var32(&MBK[0][8]);
}
else
{
Set_SCFG_Clock9(SCFG_Clock9);
Set_SCFG_MC(SCFG_MC);
DSP.SetRstLine(SCFG_RST & 0x0001);
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
file->VarArray(&mbk, sizeof(u32)*12);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
mbk[11] &= 0x00FFFF0F;
MBK[0][8] = mbk[11];
MBK[1][8] = mbk[11];
}
for (int i = 0; i < 8; i++)
NDMAs[i].DoSavestate(file);
AES.DoSavestate(file);
CamModule.DoSavestate(file);
DSP.DoSavestate(file);
I2C.DoSavestate(file);
SDMMC.DoSavestate(file);
SDIO.DoSavestate(file);
}
void DSi::SetCartInserted(bool inserted)
{
if (inserted)
SCFG_MC &= ~1;
else
SCFG_MC |= 1;
}
void DSi::DecryptModcryptArea(u32 offset, u32 size, const u8* iv)
{
AES_ctx ctx;
u8 key[16];
u8 tmp[16];
if ((offset == 0) || (size == 0))
return;
const NDSHeader& header = NDSCartSlot.GetCart()->GetHeader();
if ((header.DSiCryptoFlags & (1<<4)) ||
(header.AppFlags & (1<<7)))
{
// dev key
const u8* cartrom = NDSCartSlot.GetCart()->GetROM();
memcpy(key, &cartrom[0], 16);
}
else
{
u8 keyX[16], keyY[16];
*(u32*)&keyX[0] = 0x746E694E;
*(u32*)&keyX[4] = 0x6F646E65;
keyX[8] = header.GameCode[0];
keyX[9] = header.GameCode[1];
keyX[10] = header.GameCode[2];
keyX[11] = header.GameCode[3];
keyX[12] = header.GameCode[3];
keyX[13] = header.GameCode[2];
keyX[14] = header.GameCode[1];
keyX[15] = header.GameCode[0];
memcpy(keyY, header.DSiARM9iHash, 16);
DSi_AES::DeriveNormalKey(keyX, keyY, tmp);
}
Bswap128(key, tmp);
Bswap128(tmp, iv);
AES_init_ctx_iv(&ctx, key, tmp);
// find a matching binary area
u32 binaryaddr, binarysize;
u32 roundedsize = (size + 0xF) & ~0xF;
// CHECKME: GBAtek says the modcrypt area should be the same size, or bigger,
// than the binary area being considered
// but I have seen modcrypt areas smaller than the ARM9i binary
#define BINARY_GOOD(name) \
((offset >= header.name##ROMOffset) && \
(offset+roundedsize) <= (header.name##ROMOffset + ((header.name##Size + 0xF) & ~0xF)))
if (BINARY_GOOD(ARM9))
{
binaryaddr = header.ARM9RAMAddress;
binarysize = header.ARM9Size;
}
else if (BINARY_GOOD(ARM7))
{
binaryaddr = header.ARM7RAMAddress;
binarysize = header.ARM7Size;
}
else if (BINARY_GOOD(DSiARM9i))
{
binaryaddr = header.DSiARM9iRAMAddress;
binarysize = header.DSiARM9iSize;
}
else if (BINARY_GOOD(DSiARM7i))
{
binaryaddr = header.DSiARM7iRAMAddress;
binarysize = header.DSiARM7iSize;
}
else
return;
#undef BINARY_GOOD
for (u32 i = 0; i < size; i+=16)
{
u32 data[4];
data[0] = ARM9Read32(binaryaddr+i);
data[1] = ARM9Read32(binaryaddr+i+4);
data[2] = ARM9Read32(binaryaddr+i+8);
data[3] = ARM9Read32(binaryaddr+i+12);
Bswap128(tmp, data);
AES_CTR_xcrypt_buffer(&ctx, tmp, sizeof(tmp));
Bswap128(data, tmp);
ARM9Write32(binaryaddr+i, data[0]);
ARM9Write32(binaryaddr+i+4, data[1]);
ARM9Write32(binaryaddr+i+8, data[2]);
ARM9Write32(binaryaddr+i+12, data[3]);
}
}
void DSi::SetupDirectBoot()
{
bool dsmode = false;
NDSHeader& header = NDSCartSlot.GetCart()->GetHeader();
const u8* cartrom = NDSCartSlot.GetCart()->GetROM();
u32 cartid = NDSCartSlot.GetCart()->ID();
DSi_TSC* tsc = (DSi_TSC*)SPI.GetTSC();
// TODO: add controls for forcing DS or DSi mode?
if (!(header.UnitCode & 0x02))
dsmode = true;
if (dsmode)
{
SCFG_BIOS = 0x0303;
// no NWRAM Mapping
for (int i = 0; i < 4; i++)
MapNWRAM_A(i, 0);
for (int i = 0; i < 8; i++)
MapNWRAM_B(i, 0);
for (int i = 0; i < 8; i++)
MapNWRAM_C(i, 0);
// No NWRAM Window
for (int i = 0; i < 3; i++)
{
MapNWRAMRange(0, i, 0);
MapNWRAMRange(1, i, 0);
}
NDS::MapSharedWRAM(3);
tsc->SetMode(0x00);
Set_SCFG_Clock9(0x0000);
}
else
{
SCFG_BIOS = 0x0101;
// WRAM mapping
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
memcpy(mbk, &cartrom[0x180], 12*4);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
MBK[0][8] = mbk[11] & 0x00FFFF0F;
MBK[1][8] = mbk[11] & 0x00FFFF0F;
NDS::MapSharedWRAM(mbk[11] >> 24);
if (!(header.AppFlags & (1<<0)))
tsc->SetMode(0x00);
}
// setup main RAM data
// TODO: verify what changes when loading a DS-mode ROM
if (dsmode)
{
for (u32 i = 0; i < 0x170; i+=4)
{
u32 tmp = *(u32*)&cartrom[i];
ARM9Write32(0x027FFE00+i, tmp);
}
ARM9Write32(0x027FF800, cartid);
ARM9Write32(0x027FF804, cartid);
ARM9Write16(0x027FF808, header.HeaderCRC16);
ARM9Write16(0x027FF80A, header.SecureAreaCRC16);
ARM9Write16(0x027FF850, 0x5835);
ARM9Write32(0x027FFC00, cartid);
ARM9Write32(0x027FFC04, cartid);
ARM9Write16(0x027FFC08, header.HeaderCRC16);
ARM9Write16(0x027FFC0A, header.SecureAreaCRC16);
ARM9Write16(0x027FFC10, 0x5835);
ARM9Write16(0x027FFC30, 0xFFFF);
ARM9Write16(0x027FFC40, 0x0001);
}
else
{
// CHECKME: some of these are 'only for NDS ROM', presumably
// only for when loading a cart? (as opposed to DSiWare)
for (u32 i = 0; i < 0x160; i+=4)
{
u32 tmp = *(u32*)&cartrom[i];
ARM9Write32(0x02FFFA80+i, tmp);
ARM9Write32(0x02FFFE00+i, tmp);
}
for (u32 i = 0; i < 0x1000; i+=4)
{
u32 tmp = *(u32*)&cartrom[i];
ARM9Write32(0x02FFC000+i, tmp);
ARM9Write32(0x02FFE000+i, tmp);
}
if (DSi_NAND::NANDImage* image = SDMMC.GetNAND(); image && *image)
{ // If a NAND image is installed, and it's valid...
if (DSi_NAND::NANDMount nand = DSi_NAND::NANDMount(*image))
{
DSi_NAND::DSiFirmwareSystemSettings userdata {};
nand.ReadUserData(userdata);
for (u32 i = 0; i < 0x128; i+=4)
ARM9Write32(0x02000400+i, *(u32*)&userdata.Bytes[0x88+i]);
DSi_NAND::DSiSerialData hwinfoS {};
nand.ReadSerialData(hwinfoS);
DSi_NAND::DSiHardwareInfoN hwinfoN;
nand.ReadHardwareInfoN(hwinfoN);
for (u32 i = 0; i < 0x14; i+=4)
ARM9Write32(0x02000600+i, *(u32*)&hwinfoN[0x88+i]);
for (u32 i = 0; i < 0x18; i+=4)
ARM9Write32(0x02FFFD68+i, *(u32*)&hwinfoS.Bytes[0x88+i]);
}
}
Firmware::WifiBoard nwifiver = SPI.GetFirmware().GetHeader().WifiBoard;
ARM9Write8(0x020005E0, static_cast<u8>(nwifiver));
// TODO: these should be taken from the wifi firmware in NAND
// but, hey, this works too.
if (nwifiver == Firmware::WifiBoard::W015)
{
ARM9Write16(0x020005E2, 0xB57E);
ARM9Write32(0x020005E4, 0x00500400);
ARM9Write32(0x020005E8, 0x00500000);
ARM9Write32(0x020005EC, 0x0002E000);
}
else
{
ARM9Write16(0x020005E2, 0x5BCA);
ARM9Write32(0x020005E4, 0x00520000);
ARM9Write32(0x020005E8, 0x00520000);
ARM9Write32(0x020005EC, 0x00020000);
}
// TODO: the shit at 02FFD7B0..02FFDC00
// and some other extra shit?
ARM9Write32(0x02FFFC00, cartid);
ARM9Write16(0x02FFFC40, 0x0001); // boot indicator
ARM9Write8(0x02FFFDFA, I2C.GetBPTWL()->GetBootFlag() | 0x80);
ARM9Write8(0x02FFFDFB, 0x01);
}
// TODO: for DS-mode ROMs, switch RAM size here
u32 arm9start = 0;
// load the ARM9 secure area
if (header.ARM9ROMOffset >= 0x4000 && header.ARM9ROMOffset < 0x8000)
{
u8 securearea[0x800];
NDSCartSlot.DecryptSecureArea(securearea);
for (u32 i = 0; i < 0x800; i+=4)
{
ARM9Write32(header.ARM9RAMAddress+i, *(u32*)&securearea[i]);
arm9start += 4;
}
}
for (u32 i = arm9start; i < header.ARM9Size; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.ARM9ROMOffset+i];
ARM9Write32(header.ARM9RAMAddress+i, tmp);
}
for (u32 i = 0; i < header.ARM7Size; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.ARM7ROMOffset+i];
ARM7Write32(header.ARM7RAMAddress+i, tmp);
}
if ((!dsmode) && (header.DSiCryptoFlags & (1<<0)))
{
// load DSi-specific regions
for (u32 i = 0; i < header.DSiARM9iSize; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.DSiARM9iROMOffset+i];
ARM9Write32(header.DSiARM9iRAMAddress+i, tmp);
}
for (u32 i = 0; i < header.DSiARM7iSize; i+=4)
{
u32 tmp = *(u32*)&cartrom[header.DSiARM7iROMOffset+i];
ARM7Write32(header.DSiARM7iRAMAddress+i, tmp);
}
// decrypt any modcrypt areas
if (header.DSiCryptoFlags & (1<<1))
{
DecryptModcryptArea(header.DSiModcrypt1Offset,
header.DSiModcrypt1Size,
header.DSiARM9Hash);
DecryptModcryptArea(header.DSiModcrypt2Offset,
header.DSiModcrypt2Size,
header.DSiARM7Hash);
}
}
ARM7BIOSProt = 0x20;
SPI.GetFirmwareMem()->SetupDirectBoot();
ARM9.CP15Write(0x100, 0x00056078);
ARM9.CP15Write(0x200, 0x0000004A);
ARM9.CP15Write(0x201, 0x0000004A);
ARM9.CP15Write(0x300, 0x0000000A);
ARM9.CP15Write(0x502, 0x15111011);
ARM9.CP15Write(0x503, 0x05101011);
ARM9.CP15Write(0x600, 0x04000033);
ARM9.CP15Write(0x601, 0x04000033);
ARM9.CP15Write(0x610, 0x02000031);
ARM9.CP15Write(0x611, 0x02000031);
ARM9.CP15Write(0x620, 0x00000000);
ARM9.CP15Write(0x621, 0x00000000);
ARM9.CP15Write(0x630, 0x08000033);
ARM9.CP15Write(0x631, 0x08000033);
ARM9.CP15Write(0x640, 0x0E00001B);
ARM9.CP15Write(0x641, 0x0E00001B);
ARM9.CP15Write(0x650, 0x00000000);
ARM9.CP15Write(0x651, 0x00000000);
ARM9.CP15Write(0x660, 0xFFFF001D);
ARM9.CP15Write(0x661, 0xFFFF001D);
ARM9.CP15Write(0x670, 0x02FFC01B);
ARM9.CP15Write(0x671, 0x02FFC01B);
ARM9.CP15Write(0x910, 0x0E00000A);
ARM9.CP15Write(0x911, 0x00000020);
}
void DSi::SoftReset()
{
// TODO: check exactly what is reset
// presumably, main RAM isn't reset, since the DSi can be told
// to boot a specific title this way
// BPTWL state wouldn't be reset either since BPTWL[0x70] is
// the warmboot flag
// also, BPTWL[0x70] could be abused to quickly boot specific titles
JIT.Reset();
JIT.CheckAndInvalidateITCM();
ARM9.Reset();
ARM7.Reset();
ARM9.CP15Reset();
NDS::MapSharedWRAM(3);
// TODO: does the DSP get reset? NWRAM doesn't, so I'm assuming no
// *HOWEVER*, the bootrom (which does get rerun) does remap NWRAM, and thus
// the DSP most likely gets reset
DSP.Reset();
LoadNAND();
SDMMC.Reset();
SDIO.Reset();
AES.Reset();
if (FullBIOSBoot)
{
SCFG_BIOS = 0x0000;
}
else
{
SCFG_BIOS = 0x0101;
}
SCFG_Clock9 = 0x0187; // CHECKME
SCFG_Clock7 = 0x0187;
SCFG_EXT[0] = 0x8307F100;
SCFG_EXT[1] = 0x93FFFB06;
SCFG_MC = 0x0010;//0x0011;
// TODO: is this actually reset?
SCFG_RST = 0;
DSP.SetRstLine(false);
// LCD init flag
GPU.DispStat[0] |= (1<<6);
GPU.DispStat[1] |= (1<<6);
}
bool DSi::LoadNAND()
{
DSi_NAND::NANDImage* image = SDMMC.GetNAND();
if (!(image && *image))
{
Log(LogLevel::Error, "No NAND image loaded\n");
return false;
}
Log(LogLevel::Info, "Loading DSi NAND\n");
DSi_NAND::NANDMount nandmount(*SDMMC.GetNAND());
if (!nandmount)
{
Log(LogLevel::Error, "Failed to load DSi NAND\n");
return false;
}
FileHandle* nand = image->GetFile();
// Make sure NWRAM is accessible.
// The Bits are set to the startup values in Reset() and we might
// still have them on default (0) or some bits cleared by the previous
// run.
SCFG_EXT[0] |= (1 << 25);
SCFG_EXT[1] |= (1 << 25);
memset(NWRAM_A, 0, NWRAMSize);
memset(NWRAM_B, 0, NWRAMSize);
memset(NWRAM_C, 0, NWRAMSize);
memset(MBK, 0, sizeof(MBK));
memset(NWRAMMap_A, 0, sizeof(NWRAMMap_A));
memset(NWRAMMap_B, 0, sizeof(NWRAMMap_B));
memset(NWRAMMap_C, 0, sizeof(NWRAMMap_C));
memset(NWRAMStart, 0, sizeof(NWRAMStart));
memset(NWRAMEnd, 0, sizeof(NWRAMEnd));
memset(NWRAMMask, 0, sizeof(NWRAMMask));
u32 bootparams[8];
if (FullBIOSBoot)
{
// TODO: figure out default MBK mapping
// MBK1..5: disable mappings
for (int i = 0; i < 8; ++i)
{
if (i < 4)
MapNWRAM_A(i, 0);
MapNWRAM_B(i, 0);
MapNWRAM_C(i, 0);
}
// MBK6..8: address mappings: nothing mapped
for (int i = 0; i < 6; ++i)
{
MapNWRAMRange(i & 1, i >> 1, 0);
}
// MBK9: ARM9 allowed to write
MBK[0][8] = 0;
MBK[1][8] = 0;
}
else
{
FileSeek(nand, 0x220, FileSeekOrigin::Start);
FileRead(bootparams, 4, 8, nand);
Log(LogLevel::Debug, "ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
Log(LogLevel::Debug, "ARM7: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
bootparams[4], bootparams[5], bootparams[6], bootparams[7]);
// read and apply new-WRAM settings
MBK[0][8] = 0;
MBK[1][8] = 0;
u32 mbk[12];
FileSeek(nand, 0x380, FileSeekOrigin::Start);
FileRead(mbk, 4, 12, nand);
MapNWRAM_A(0, mbk[0] & 0xFF);
MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
MapNWRAM_A(3, mbk[0] >> 24);
MapNWRAM_B(0, mbk[1] & 0xFF);
MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
MapNWRAM_B(3, mbk[1] >> 24);
MapNWRAM_B(4, mbk[2] & 0xFF);
MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
MapNWRAM_B(7, mbk[2] >> 24);
MapNWRAM_C(0, mbk[3] & 0xFF);
MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
MapNWRAM_C(3, mbk[3] >> 24);
MapNWRAM_C(4, mbk[4] & 0xFF);
MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
MapNWRAM_C(7, mbk[4] >> 24);
MapNWRAMRange(0, 0, mbk[5]);
MapNWRAMRange(0, 1, mbk[6]);
MapNWRAMRange(0, 2, mbk[7]);
MapNWRAMRange(1, 0, mbk[8]);
MapNWRAMRange(1, 1, mbk[9]);
MapNWRAMRange(1, 2, mbk[10]);
// TODO: find out why it is 0xFF000000
mbk[11] &= 0x00FFFF0F;
MBK[0][8] = mbk[11];
MBK[1][8] = mbk[11];
// load boot2 binaries
AES_ctx ctx;
const u8 boot2key[16] = {0xAD, 0x34, 0xEC, 0xF9, 0x62, 0x6E, 0xC2, 0x3A, 0xF6, 0xB4, 0x6C, 0x00, 0x80, 0x80, 0xEE, 0x98};
u8 boot2iv[16];
u8 tmp[16];
u32 dstaddr;
*(u32*)&tmp[0] = bootparams[3];
*(u32*)&tmp[4] = -bootparams[3];
*(u32*)&tmp[8] = ~bootparams[3];
*(u32*)&tmp[12] = 0;
Bswap128(boot2iv, tmp);
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
FileSeek(nand, bootparams[0], FileSeekOrigin::Start);
dstaddr = bootparams[2];
for (u32 i = 0; i < bootparams[3]; i += 16)
{
u32 data[4];
FileRead(data, 16, 1, nand);
Bswap128(tmp, data);
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
Bswap128(data, tmp);
ARM9Write32(dstaddr, data[0]); dstaddr += 4;
ARM9Write32(dstaddr, data[1]); dstaddr += 4;
ARM9Write32(dstaddr, data[2]); dstaddr += 4;
ARM9Write32(dstaddr, data[3]); dstaddr += 4;
}
*(u32*)&tmp[0] = bootparams[7];
*(u32*)&tmp[4] = -bootparams[7];
*(u32*)&tmp[8] = ~bootparams[7];
*(u32*)&tmp[12] = 0;
Bswap128(boot2iv, tmp);
AES_init_ctx_iv(&ctx, boot2key, boot2iv);
FileSeek(nand, bootparams[4], FileSeekOrigin::Start);
dstaddr = bootparams[6];
for (u32 i = 0; i < bootparams[7]; i += 16)
{
u32 data[4];
FileRead(data, 16, 1, nand);
Bswap128(tmp, data);
AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
Bswap128(data, tmp);
ARM7Write32(dstaddr, data[0]); dstaddr += 4;
ARM7Write32(dstaddr, data[1]); dstaddr += 4;
ARM7Write32(dstaddr, data[2]); dstaddr += 4;
ARM7Write32(dstaddr, data[3]); dstaddr += 4;
}
}
const DSi_NAND::DSiKey& emmccid = image->GetEMMCID();
Log(LogLevel::Debug, "eMMC CID: %08llX%08llX\n", *(const u64*)&emmccid[0], *(const u64*)&emmccid[8]);
Log(LogLevel::Debug, "Console ID: %" PRIx64 "\n", image->GetConsoleID());
if (FullBIOSBoot)
{
// point CPUs to boot ROM reset vectors
ARM9.JumpTo(0xFFFF0000);
ARM7.JumpTo(0x00000000);
}
else
{
u32 eaddr = 0x03FFE6E4;
ARM7Write32(eaddr+0x00, *(const u32*)&emmccid[0]);
ARM7Write32(eaddr+0x04, *(const u32*)&emmccid[4]);
ARM7Write32(eaddr+0x08, *(const u32*)&emmccid[8]);
ARM7Write32(eaddr+0x0C, *(const u32*)&emmccid[12]);
ARM7Write16(eaddr+0x2C, 0x0001);
ARM7Write16(eaddr+0x2E, 0x0001);
ARM7Write16(eaddr+0x3C, 0x0100);
ARM7Write16(eaddr+0x3E, 0x40E0);
ARM7Write16(eaddr+0x42, 0x0001);
memcpy(&ARM9.ITCM[0x4400], &ARM9iBIOS[0x87F4], 0x400);
memcpy(&ARM9.ITCM[0x4800], &ARM9iBIOS[0x9920], 0x80);
memcpy(&ARM9.ITCM[0x4894], &ARM9iBIOS[0x99A0], 0x1048);
memcpy(&ARM9.ITCM[0x58DC], &ARM9iBIOS[0xA9E8], 0x1048);
u8 ARM7Init[0x3C00];
memset(ARM7Init, 0, 0x3C00);
memcpy(&ARM7Init[0x0000], &ARM7iBIOS[0x8188], 0x200);
memcpy(&ARM7Init[0x0200], &ARM7iBIOS[0xB5D8], 0x40);
memcpy(&ARM7Init[0x0254], &ARM7iBIOS[0xC6D0], 0x1048);
memcpy(&ARM7Init[0x129C], &ARM7iBIOS[0xD718], 0x1048);
for (u32 i = 0; i < 0x3C00; i+=4)
ARM7Write32(0x03FFC400+i, *(u32*)&ARM7Init[i]);
// repoint the CPUs to the boot2 binaries
ARM9.JumpTo(bootparams[2]);
ARM7.JumpTo(bootparams[6]);
}
// user data is now expected to be patched by the frontend
return true;
}
void DSi::RunNDMAs(u32 cpu)
{
// TODO: round-robin mode (requires DMA channels to have a subblock delay set)
if (cpu == 0)
{
if (ARM9Timestamp >= ARM9Target) return;
if (!(CPUStop & CPUStop_GXStall)) NDMAs[0].Run();
if (!(CPUStop & CPUStop_GXStall)) NDMAs[1].Run();
if (!(CPUStop & CPUStop_GXStall)) NDMAs[2].Run();
if (!(CPUStop & CPUStop_GXStall)) NDMAs[3].Run();
}
else
{
if (ARM7Timestamp >= ARM7Target) return;
NDMAs[4].Run();
NDMAs[5].Run();
NDMAs[6].Run();
NDMAs[7].Run();
}
}
void DSi::StallNDMAs()
{
// TODO
}
bool DSi::DMAsInMode(u32 cpu, u32 mode) const
{
if (NDS::DMAsInMode(cpu, mode)) return true;
return NDMAsInMode(cpu, NDMAModes[mode]);
}
bool DSi::DMAsRunning(u32 cpu) const
{
if (NDS::DMAsRunning(cpu)) return true;
return NDMAsRunning(cpu);
}
bool DSi::NDMAsInMode(u32 cpu, u32 mode) const
{
cpu <<= 2;
if (NDMAs[cpu+0].IsInMode(mode)) return true;
if (NDMAs[cpu+1].IsInMode(mode)) return true;
if (NDMAs[cpu+2].IsInMode(mode)) return true;
if (NDMAs[cpu+3].IsInMode(mode)) return true;