A minimal GPU design in Verilog to learn how GPUs work from the ground up

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

RSD: RISC-V Out-of-Order Superscalar Processor

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

A directory of Western Digital’s RISC-V SweRV Cores

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Tile based architecture designed for computing efficiency, scalability and generality

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Network on Chip Implementation written in SytemVerilog

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

Generic Register Interface (contains various adapters)

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters