IEEE 802.16 OFDM-based transceiver system

Software defined radio receiver powered by GNU Radio and Qt.

IEEE 802.11 OFDM-based transceiver system

Deep learning toolkit-enabled VLSI placement

The Delite Git Repo

Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"

GNSS-SDR, an open-source software-defined GNSS receiver

HIP: C++ Heterogeneous-Compute Interface for Portability

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

An open source GPU based off of the AMD Southern Islands ISA.

A minimal GPU design in Verilog to learn how GPUs work from the ground up

An rv32i inspired ISA, SIMT GPU implementation in system-verilog.

Low Level Hardware Description — A foundation for building hardware design tools.

An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).

CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.

An Open-Source Tool for CGRA Accelerators

an educational compiler intermediate representation

OpenTitan: Open source silicon root of trust

Generic Register Interface (contains various adapters)

RISC-V Zve32x Vector Coprocessor

'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

RISC-V Formal Verification Framework

OpenSoC Fabric - A Network-On-Chip Generator

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters