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Collect some CS textbooks for learning.

SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol

Implementing a snoopy cache coherence for dual core processor with MSI protocol using Verilog HDL

The MiBench testsuite, extended for use in general embedded environments

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

Awesome algorithm refactor from 'Algorithm 4th Edition'

This respository is the C++ version of algs4.

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

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RISC-V System on Chip Template

Verilog Configurable Cache

A small C compiler

Simple multicore processor implemented in VHDL

DUTH RISC-V Microprocessor

A graphical processor simulator and assembly editor for the RISC-V ISA

VRoom! RISC-V CPU

Instruction set simulator for RISC-V, MIPS and ARM-v6m

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

GPGPU microprocessor architecture

Build your hardware, easily!

128KB AXI cache (32-bit in, 256-bit out)

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

Simple 3-stage pipeline RISC-V processor

biRISC-V - 32-bit dual issue RISC-V CPU Software Environment

DUTH RISC-V Superscalar Microprocessor

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.