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af9013.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Afatech AF9013 demodulator driver
*
* Copyright (C) 2007 Antti Palosaari <[email protected]>
* Copyright (C) 2011 Antti Palosaari <[email protected]>
*
* Thanks to Afatech who kindly provided information.
*/
#include "af9013_priv.h"
struct af9013_state {
struct i2c_client *client;
struct regmap *regmap;
struct i2c_mux_core *muxc;
struct dvb_frontend fe;
u32 clk;
u8 tuner;
u32 if_frequency;
u8 ts_mode;
u8 ts_output_pin;
bool spec_inv;
u8 api_version[4];
u8 gpio[4];
u32 bandwidth_hz;
enum fe_status fe_status;
/* RF and IF AGC limits used for signal strength calc */
u8 strength_en, rf_agc_50, rf_agc_80, if_agc_50, if_agc_80;
unsigned long set_frontend_jiffies;
unsigned long read_status_jiffies;
unsigned long strength_jiffies;
unsigned long cnr_jiffies;
unsigned long ber_ucb_jiffies;
u16 dvbv3_snr;
u16 dvbv3_strength;
u32 dvbv3_ber;
u32 dvbv3_ucblocks;
bool first_tune;
};
static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
{
struct i2c_client *client = state->client;
int ret;
u8 pos;
u16 addr;
dev_dbg(&client->dev, "gpio %u, gpioval %02x\n", gpio, gpioval);
/*
* GPIO0 & GPIO1 0xd735
* GPIO2 & GPIO3 0xd736
*/
switch (gpio) {
case 0:
case 1:
addr = 0xd735;
break;
case 2:
case 3:
addr = 0xd736;
break;
default:
ret = -EINVAL;
goto err;
}
switch (gpio) {
case 0:
case 2:
pos = 0;
break;
case 1:
case 3:
default:
pos = 4;
break;
}
ret = regmap_update_bits(state->regmap, addr, 0x0f << pos,
gpioval << pos);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *fesettings)
{
fesettings->min_delay_ms = 800;
fesettings->step_size = 0;
fesettings->max_drift = 0;
return 0;
}
static int af9013_set_frontend(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, i, sampling_freq;
bool auto_mode, spec_inv;
u8 buf[6];
u32 if_frequency, freq_cw;
dev_dbg(&client->dev, "frequency %u, bandwidth_hz %u\n",
c->frequency, c->bandwidth_hz);
/* program tuner */
if (fe->ops.tuner_ops.set_params) {
ret = fe->ops.tuner_ops.set_params(fe);
if (ret)
goto err;
}
/* program CFOE coefficients */
if (c->bandwidth_hz != state->bandwidth_hz) {
for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
if (coeff_lut[i].clock == state->clk &&
coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
break;
}
}
/* Return an error if can't find bandwidth or the right clock */
if (i == ARRAY_SIZE(coeff_lut)) {
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_write(state->regmap, 0xae00, coeff_lut[i].val,
sizeof(coeff_lut[i].val));
if (ret)
goto err;
}
/* program frequency control */
if (c->bandwidth_hz != state->bandwidth_hz || state->first_tune) {
/* get used IF frequency */
if (fe->ops.tuner_ops.get_if_frequency) {
ret = fe->ops.tuner_ops.get_if_frequency(fe,
&if_frequency);
if (ret)
goto err;
} else {
if_frequency = state->if_frequency;
}
dev_dbg(&client->dev, "if_frequency %u\n", if_frequency);
sampling_freq = if_frequency;
while (sampling_freq > (state->clk / 2))
sampling_freq -= state->clk;
if (sampling_freq < 0) {
sampling_freq *= -1;
spec_inv = state->spec_inv;
} else {
spec_inv = !state->spec_inv;
}
freq_cw = DIV_ROUND_CLOSEST_ULL((u64)sampling_freq * 0x800000,
state->clk);
if (spec_inv)
freq_cw = 0x800000 - freq_cw;
buf[0] = (freq_cw >> 0) & 0xff;
buf[1] = (freq_cw >> 8) & 0xff;
buf[2] = (freq_cw >> 16) & 0x7f;
freq_cw = 0x800000 - freq_cw;
buf[3] = (freq_cw >> 0) & 0xff;
buf[4] = (freq_cw >> 8) & 0xff;
buf[5] = (freq_cw >> 16) & 0x7f;
ret = regmap_bulk_write(state->regmap, 0xd140, buf, 3);
if (ret)
goto err;
ret = regmap_bulk_write(state->regmap, 0x9be7, buf, 6);
if (ret)
goto err;
}
/* clear TPS lock flag */
ret = regmap_update_bits(state->regmap, 0xd330, 0x08, 0x08);
if (ret)
goto err;
/* clear MPEG2 lock flag */
ret = regmap_update_bits(state->regmap, 0xd507, 0x40, 0x00);
if (ret)
goto err;
/* empty channel function */
ret = regmap_update_bits(state->regmap, 0x9bfe, 0x01, 0x00);
if (ret)
goto err;
/* empty DVB-T channel function */
ret = regmap_update_bits(state->regmap, 0x9bc2, 0x01, 0x00);
if (ret)
goto err;
/* transmission parameters */
auto_mode = false;
memset(buf, 0, 3);
switch (c->transmission_mode) {
case TRANSMISSION_MODE_AUTO:
auto_mode = true;
break;
case TRANSMISSION_MODE_2K:
break;
case TRANSMISSION_MODE_8K:
buf[0] |= (1 << 0);
break;
default:
dev_dbg(&client->dev, "invalid transmission_mode\n");
auto_mode = true;
}
switch (c->guard_interval) {
case GUARD_INTERVAL_AUTO:
auto_mode = true;
break;
case GUARD_INTERVAL_1_32:
break;
case GUARD_INTERVAL_1_16:
buf[0] |= (1 << 2);
break;
case GUARD_INTERVAL_1_8:
buf[0] |= (2 << 2);
break;
case GUARD_INTERVAL_1_4:
buf[0] |= (3 << 2);
break;
default:
dev_dbg(&client->dev, "invalid guard_interval\n");
auto_mode = true;
}
switch (c->hierarchy) {
case HIERARCHY_AUTO:
auto_mode = true;
break;
case HIERARCHY_NONE:
break;
case HIERARCHY_1:
buf[0] |= (1 << 4);
break;
case HIERARCHY_2:
buf[0] |= (2 << 4);
break;
case HIERARCHY_4:
buf[0] |= (3 << 4);
break;
default:
dev_dbg(&client->dev, "invalid hierarchy\n");
auto_mode = true;
}
switch (c->modulation) {
case QAM_AUTO:
auto_mode = true;
break;
case QPSK:
break;
case QAM_16:
buf[1] |= (1 << 6);
break;
case QAM_64:
buf[1] |= (2 << 6);
break;
default:
dev_dbg(&client->dev, "invalid modulation\n");
auto_mode = true;
}
/* Use HP. How and which case we can switch to LP? */
buf[1] |= (1 << 4);
switch (c->code_rate_HP) {
case FEC_AUTO:
auto_mode = true;
break;
case FEC_1_2:
break;
case FEC_2_3:
buf[2] |= (1 << 0);
break;
case FEC_3_4:
buf[2] |= (2 << 0);
break;
case FEC_5_6:
buf[2] |= (3 << 0);
break;
case FEC_7_8:
buf[2] |= (4 << 0);
break;
default:
dev_dbg(&client->dev, "invalid code_rate_HP\n");
auto_mode = true;
}
switch (c->code_rate_LP) {
case FEC_AUTO:
auto_mode = true;
break;
case FEC_1_2:
break;
case FEC_2_3:
buf[2] |= (1 << 3);
break;
case FEC_3_4:
buf[2] |= (2 << 3);
break;
case FEC_5_6:
buf[2] |= (3 << 3);
break;
case FEC_7_8:
buf[2] |= (4 << 3);
break;
case FEC_NONE:
break;
default:
dev_dbg(&client->dev, "invalid code_rate_LP\n");
auto_mode = true;
}
switch (c->bandwidth_hz) {
case 6000000:
break;
case 7000000:
buf[1] |= (1 << 2);
break;
case 8000000:
buf[1] |= (2 << 2);
break;
default:
dev_dbg(&client->dev, "invalid bandwidth_hz\n");
ret = -EINVAL;
goto err;
}
ret = regmap_bulk_write(state->regmap, 0xd3c0, buf, 3);
if (ret)
goto err;
if (auto_mode) {
/* clear easy mode flag */
ret = regmap_write(state->regmap, 0xaefd, 0x00);
if (ret)
goto err;
dev_dbg(&client->dev, "auto params\n");
} else {
/* set easy mode flag */
ret = regmap_write(state->regmap, 0xaefd, 0x01);
if (ret)
goto err;
ret = regmap_write(state->regmap, 0xaefe, 0x00);
if (ret)
goto err;
dev_dbg(&client->dev, "manual params\n");
}
/* Reset FSM */
ret = regmap_write(state->regmap, 0xffff, 0x00);
if (ret)
goto err;
state->bandwidth_hz = c->bandwidth_hz;
state->set_frontend_jiffies = jiffies;
state->first_tune = false;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_get_frontend(struct dvb_frontend *fe,
struct dtv_frontend_properties *c)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
u8 buf[3];
dev_dbg(&client->dev, "\n");
ret = regmap_bulk_read(state->regmap, 0xd3c0, buf, 3);
if (ret)
goto err;
switch ((buf[1] >> 6) & 3) {
case 0:
c->modulation = QPSK;
break;
case 1:
c->modulation = QAM_16;
break;
case 2:
c->modulation = QAM_64;
break;
}
switch ((buf[0] >> 0) & 3) {
case 0:
c->transmission_mode = TRANSMISSION_MODE_2K;
break;
case 1:
c->transmission_mode = TRANSMISSION_MODE_8K;
}
switch ((buf[0] >> 2) & 3) {
case 0:
c->guard_interval = GUARD_INTERVAL_1_32;
break;
case 1:
c->guard_interval = GUARD_INTERVAL_1_16;
break;
case 2:
c->guard_interval = GUARD_INTERVAL_1_8;
break;
case 3:
c->guard_interval = GUARD_INTERVAL_1_4;
break;
}
switch ((buf[0] >> 4) & 7) {
case 0:
c->hierarchy = HIERARCHY_NONE;
break;
case 1:
c->hierarchy = HIERARCHY_1;
break;
case 2:
c->hierarchy = HIERARCHY_2;
break;
case 3:
c->hierarchy = HIERARCHY_4;
break;
}
switch ((buf[2] >> 0) & 7) {
case 0:
c->code_rate_HP = FEC_1_2;
break;
case 1:
c->code_rate_HP = FEC_2_3;
break;
case 2:
c->code_rate_HP = FEC_3_4;
break;
case 3:
c->code_rate_HP = FEC_5_6;
break;
case 4:
c->code_rate_HP = FEC_7_8;
break;
}
switch ((buf[2] >> 3) & 7) {
case 0:
c->code_rate_LP = FEC_1_2;
break;
case 1:
c->code_rate_LP = FEC_2_3;
break;
case 2:
c->code_rate_LP = FEC_3_4;
break;
case 3:
c->code_rate_LP = FEC_5_6;
break;
case 4:
c->code_rate_LP = FEC_7_8;
break;
}
switch ((buf[1] >> 2) & 3) {
case 0:
c->bandwidth_hz = 6000000;
break;
case 1:
c->bandwidth_hz = 7000000;
break;
case 2:
c->bandwidth_hz = 8000000;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int ret, stmp1;
unsigned int utmp, utmp1, utmp2, utmp3, utmp4;
u8 buf[7];
dev_dbg(&client->dev, "\n");
/*
* Return status from the cache if it is younger than 2000ms with the
* exception of last tune is done during 4000ms.
*/
if (time_is_after_jiffies(state->read_status_jiffies + msecs_to_jiffies(2000)) &&
time_is_before_jiffies(state->set_frontend_jiffies + msecs_to_jiffies(4000))) {
*status = state->fe_status;
} else {
/* MPEG2 lock */
ret = regmap_read(state->regmap, 0xd507, &utmp);
if (ret)
goto err;
if ((utmp >> 6) & 0x01) {
utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
} else {
/* TPS lock */
ret = regmap_read(state->regmap, 0xd330, &utmp);
if (ret)
goto err;
if ((utmp >> 3) & 0x01)
utmp1 = FE_HAS_SIGNAL | FE_HAS_CARRIER |
FE_HAS_VITERBI;
else
utmp1 = 0;
}
dev_dbg(&client->dev, "fe_status %02x\n", utmp1);
state->read_status_jiffies = jiffies;
state->fe_status = utmp1;
*status = utmp1;
}
/* Signal strength */
switch (state->strength_en) {
case 0:
/* Check if we support signal strength */
ret = regmap_read(state->regmap, 0x9bee, &utmp);
if (ret)
goto err;
if ((utmp >> 0) & 0x01) {
/* Read agc values for signal strength estimation */
ret = regmap_read(state->regmap, 0x9bbd, &utmp1);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9bd0, &utmp2);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9be2, &utmp3);
if (ret)
goto err;
ret = regmap_read(state->regmap, 0x9be4, &utmp4);
if (ret)
goto err;
state->rf_agc_50 = utmp1;
state->rf_agc_80 = utmp2;
state->if_agc_50 = utmp3;
state->if_agc_80 = utmp4;
dev_dbg(&client->dev,
"rf_agc_50 %u, rf_agc_80 %u, if_agc_50 %u, if_agc_80 %u\n",
utmp1, utmp2, utmp3, utmp4);
state->strength_en = 1;
} else {
/* Signal strength is not supported */
state->strength_en = 2;
break;
}
fallthrough;
case 1:
if (time_is_after_jiffies(state->strength_jiffies + msecs_to_jiffies(2000)))
break;
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd07c, buf, 2);
if (ret)
goto err;
/*
* Construct line equation from tuner dependent -80/-50 dBm agc
* limits and use it to map current agc value to dBm estimate
*/
#define agc_gain (buf[0] + buf[1])
#define agc_gain_50dbm (state->rf_agc_50 + state->if_agc_50)
#define agc_gain_80dbm (state->rf_agc_80 + state->if_agc_80)
stmp1 = 30000 * (agc_gain - agc_gain_80dbm) /
(agc_gain_50dbm - agc_gain_80dbm) - 80000;
dev_dbg(&client->dev,
"strength %d, agc_gain %d, agc_gain_50dbm %d, agc_gain_80dbm %d\n",
stmp1, agc_gain, agc_gain_50dbm, agc_gain_80dbm);
state->strength_jiffies = jiffies;
/* Convert [-90, -30] dBm to [0x0000, 0xffff] for dvbv3 */
utmp1 = clamp(stmp1 + 90000, 0, 60000);
state->dvbv3_strength = div_u64((u64)utmp1 * 0xffff, 60000);
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
c->strength.stat[0].svalue = stmp1;
break;
default:
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
/* CNR */
switch (state->fe_status & FE_HAS_VITERBI) {
case FE_HAS_VITERBI:
if (time_is_after_jiffies(state->cnr_jiffies + msecs_to_jiffies(2000)))
break;
/* Check if cnr ready */
ret = regmap_read(state->regmap, 0xd2e1, &utmp);
if (ret)
goto err;
if (!((utmp >> 3) & 0x01)) {
dev_dbg(&client->dev, "cnr not ready\n");
break;
}
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd2e3, buf, 3);
if (ret)
goto err;
utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
/* Read current modulation */
ret = regmap_read(state->regmap, 0xd3c1, &utmp);
if (ret)
goto err;
switch ((utmp >> 6) & 3) {
case 0:
/*
* QPSK
* CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
* value [653799, 1689999], 2.6 / 13 = 3355443
*/
utmp1 = clamp(utmp1, 653799U, 1689999U);
utmp1 = ((u64)(intlog10(utmp1)
- intlog10(1690000 - utmp1)
+ 3355443) * 13 * 1000) >> 24;
break;
case 1:
/*
* QAM-16
* CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
* value [371105, 827999], 15.7 / 6 = 43900382
*/
utmp1 = clamp(utmp1, 371105U, 827999U);
utmp1 = ((u64)(intlog10(utmp1 - 370000)
- intlog10(828000 - utmp1)
+ 43900382) * 6 * 1000) >> 24;
break;
case 2:
/*
* QAM-64
* CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
* value [193246, 424999], 23.8 / 8 = 49912218
*/
utmp1 = clamp(utmp1, 193246U, 424999U);
utmp1 = ((u64)(intlog10(utmp1 - 193000)
- intlog10(425000 - utmp1)
+ 49912218) * 8 * 1000) >> 24;
break;
default:
dev_dbg(&client->dev, "invalid modulation %u\n",
(utmp >> 6) & 3);
utmp1 = 0;
break;
}
dev_dbg(&client->dev, "cnr %u\n", utmp1);
state->cnr_jiffies = jiffies;
state->dvbv3_snr = utmp1 / 100;
c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
c->cnr.stat[0].svalue = utmp1;
break;
default:
c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
/* BER / PER */
switch (state->fe_status & FE_HAS_SYNC) {
case FE_HAS_SYNC:
if (time_is_after_jiffies(state->ber_ucb_jiffies + msecs_to_jiffies(2000)))
break;
/* Check if ber / ucb is ready */
ret = regmap_read(state->regmap, 0xd391, &utmp);
if (ret)
goto err;
if (!((utmp >> 4) & 0x01)) {
dev_dbg(&client->dev, "ber not ready\n");
break;
}
/* Read value */
ret = regmap_bulk_read(state->regmap, 0xd385, buf, 7);
if (ret)
goto err;
utmp1 = buf[4] << 16 | buf[3] << 8 | buf[2] << 0;
utmp2 = (buf[1] << 8 | buf[0] << 0) * 204 * 8;
utmp3 = buf[6] << 8 | buf[5] << 0;
utmp4 = buf[1] << 8 | buf[0] << 0;
/* Use 10000 TS packets for measure */
if (utmp4 != 10000) {
buf[0] = (10000 >> 0) & 0xff;
buf[1] = (10000 >> 8) & 0xff;
ret = regmap_bulk_write(state->regmap, 0xd385, buf, 2);
if (ret)
goto err;
}
/* Reset ber / ucb counter */
ret = regmap_update_bits(state->regmap, 0xd391, 0x20, 0x20);
if (ret)
goto err;
dev_dbg(&client->dev, "post_bit_error %u, post_bit_count %u\n",
utmp1, utmp2);
dev_dbg(&client->dev, "block_error %u, block_count %u\n",
utmp3, utmp4);
state->ber_ucb_jiffies = jiffies;
state->dvbv3_ber = utmp1;
state->dvbv3_ucblocks += utmp3;
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_error.stat[0].uvalue += utmp1;
c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
c->post_bit_count.stat[0].uvalue += utmp2;
c->block_error.stat[0].scale = FE_SCALE_COUNTER;
c->block_error.stat[0].uvalue += utmp3;
c->block_count.stat[0].scale = FE_SCALE_COUNTER;
c->block_count.stat[0].uvalue += utmp4;
break;
default:
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
break;
}
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct af9013_state *state = fe->demodulator_priv;
*snr = state->dvbv3_snr;
return 0;
}
static int af9013_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct af9013_state *state = fe->demodulator_priv;
*strength = state->dvbv3_strength;
return 0;
}
static int af9013_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct af9013_state *state = fe->demodulator_priv;
*ber = state->dvbv3_ber;
return 0;
}
static int af9013_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct af9013_state *state = fe->demodulator_priv;
*ucblocks = state->dvbv3_ucblocks;
return 0;
}
static int af9013_init(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret, i, len;
unsigned int utmp;
u8 buf[3];
const struct af9013_reg_mask_val *tab;
dev_dbg(&client->dev, "\n");
/* ADC on */
ret = regmap_update_bits(state->regmap, 0xd73a, 0x08, 0x00);
if (ret)
goto err;
/* Clear reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x02, 0x00);
if (ret)
goto err;
/* Disable reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x00);
if (ret)
goto err;
/* write API version to firmware */
ret = regmap_bulk_write(state->regmap, 0x9bf2, state->api_version, 4);
if (ret)
goto err;
/* program ADC control */
switch (state->clk) {
case 28800000: /* 28.800 MHz */
utmp = 0;
break;
case 20480000: /* 20.480 MHz */
utmp = 1;
break;
case 28000000: /* 28.000 MHz */
utmp = 2;
break;
case 25000000: /* 25.000 MHz */
utmp = 3;
break;
default:
ret = -EINVAL;
goto err;
}
ret = regmap_update_bits(state->regmap, 0x9bd2, 0x0f, utmp);
if (ret)
goto err;
utmp = div_u64((u64)state->clk * 0x80000, 1000000);
buf[0] = (utmp >> 0) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 16) & 0xff;
ret = regmap_bulk_write(state->regmap, 0xd180, buf, 3);
if (ret)
goto err;
/* Demod core settings */
dev_dbg(&client->dev, "load demod core settings\n");
len = ARRAY_SIZE(demod_init_tab);
tab = demod_init_tab;
for (i = 0; i < len; i++) {
ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
/* Demod tuner specific settings */
dev_dbg(&client->dev, "load tuner specific settings\n");
switch (state->tuner) {
case AF9013_TUNER_MXL5003D:
len = ARRAY_SIZE(tuner_init_tab_mxl5003d);
tab = tuner_init_tab_mxl5003d;
break;
case AF9013_TUNER_MXL5005D:
case AF9013_TUNER_MXL5005R:
case AF9013_TUNER_MXL5007T:
len = ARRAY_SIZE(tuner_init_tab_mxl5005);
tab = tuner_init_tab_mxl5005;
break;
case AF9013_TUNER_ENV77H11D5:
len = ARRAY_SIZE(tuner_init_tab_env77h11d5);
tab = tuner_init_tab_env77h11d5;
break;
case AF9013_TUNER_MT2060:
len = ARRAY_SIZE(tuner_init_tab_mt2060);
tab = tuner_init_tab_mt2060;
break;
case AF9013_TUNER_MC44S803:
len = ARRAY_SIZE(tuner_init_tab_mc44s803);
tab = tuner_init_tab_mc44s803;
break;
case AF9013_TUNER_QT1010:
case AF9013_TUNER_QT1010A:
len = ARRAY_SIZE(tuner_init_tab_qt1010);
tab = tuner_init_tab_qt1010;
break;
case AF9013_TUNER_MT2060_2:
len = ARRAY_SIZE(tuner_init_tab_mt2060_2);
tab = tuner_init_tab_mt2060_2;
break;
case AF9013_TUNER_TDA18271:
case AF9013_TUNER_TDA18218:
len = ARRAY_SIZE(tuner_init_tab_tda18271);
tab = tuner_init_tab_tda18271;
break;
case AF9013_TUNER_UNKNOWN:
default:
len = ARRAY_SIZE(tuner_init_tab_unknown);
tab = tuner_init_tab_unknown;
break;
}
for (i = 0; i < len; i++) {
ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask,
tab[i].val);
if (ret)
goto err;
}
/* TS interface */
if (state->ts_output_pin == 7)
utmp = 1 << 3 | state->ts_mode << 1;
else
utmp = 0 << 3 | state->ts_mode << 1;
ret = regmap_update_bits(state->regmap, 0xd500, 0x0e, utmp);
if (ret)
goto err;
/* enable lock led */
ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x01);
if (ret)
goto err;
state->first_tune = true;
return 0;
err:
dev_dbg(&client->dev, "failed %d\n", ret);
return ret;
}
static int af9013_sleep(struct dvb_frontend *fe)
{
struct af9013_state *state = fe->demodulator_priv;
struct i2c_client *client = state->client;
int ret;
unsigned int utmp;
dev_dbg(&client->dev, "\n");
/* disable lock led */
ret = regmap_update_bits(state->regmap, 0xd730, 0x01, 0x00);
if (ret)
goto err;
/* Enable reset */
ret = regmap_update_bits(state->regmap, 0xd417, 0x10, 0x10);
if (ret)
goto err;
/* Start reset execution */
ret = regmap_write(state->regmap, 0xaeff, 0x01);
if (ret)
goto err;