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imx290.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Sony IMX290 CMOS Image Sensor Driver
*
* Copyright (C) 2019 FRAMOS GmbH.
*
* Copyright (C) 2019 Linaro Ltd.
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/unaligned.h>
#include <media/media-entity.h>
#include <media/v4l2-cci.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#define IMX290_STANDBY CCI_REG8(0x3000)
#define IMX290_REGHOLD CCI_REG8(0x3001)
#define IMX290_XMSTA CCI_REG8(0x3002)
#define IMX290_ADBIT CCI_REG8(0x3005)
#define IMX290_ADBIT_10BIT (0 << 0)
#define IMX290_ADBIT_12BIT (1 << 0)
#define IMX290_CTRL_07 CCI_REG8(0x3007)
#define IMX290_VREVERSE BIT(0)
#define IMX290_HREVERSE BIT(1)
#define IMX290_WINMODE_1080P (0 << 4)
#define IMX290_WINMODE_720P (1 << 4)
#define IMX290_WINMODE_CROP (4 << 4)
#define IMX290_FR_FDG_SEL CCI_REG8(0x3009)
#define IMX290_BLKLEVEL CCI_REG16_LE(0x300a)
#define IMX290_GAIN CCI_REG8(0x3014)
#define IMX290_VMAX CCI_REG24_LE(0x3018)
#define IMX290_VMAX_MAX 0x3ffff
#define IMX290_HMAX CCI_REG16_LE(0x301c)
#define IMX290_HMAX_MAX 0xffff
#define IMX290_SHS1 CCI_REG24_LE(0x3020)
#define IMX290_WINWV_OB CCI_REG8(0x303a)
#define IMX290_WINPV CCI_REG16_LE(0x303c)
#define IMX290_WINWV CCI_REG16_LE(0x303e)
#define IMX290_WINPH CCI_REG16_LE(0x3040)
#define IMX290_WINWH CCI_REG16_LE(0x3042)
#define IMX290_OUT_CTRL CCI_REG8(0x3046)
#define IMX290_ODBIT_10BIT (0 << 0)
#define IMX290_ODBIT_12BIT (1 << 0)
#define IMX290_OPORTSEL_PARALLEL (0x0 << 4)
#define IMX290_OPORTSEL_LVDS_2CH (0xd << 4)
#define IMX290_OPORTSEL_LVDS_4CH (0xe << 4)
#define IMX290_OPORTSEL_LVDS_8CH (0xf << 4)
#define IMX290_XSOUTSEL CCI_REG8(0x304b)
#define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0)
#define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0)
#define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2)
#define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2)
#define IMX290_INCKSEL1 CCI_REG8(0x305c)
#define IMX290_INCKSEL2 CCI_REG8(0x305d)
#define IMX290_INCKSEL3 CCI_REG8(0x305e)
#define IMX290_INCKSEL4 CCI_REG8(0x305f)
#define IMX290_PGCTRL CCI_REG8(0x308c)
#define IMX290_ADBIT1 CCI_REG8(0x3129)
#define IMX290_ADBIT1_10BIT 0x1d
#define IMX290_ADBIT1_12BIT 0x00
#define IMX290_INCKSEL5 CCI_REG8(0x315e)
#define IMX290_INCKSEL6 CCI_REG8(0x3164)
#define IMX290_ADBIT2 CCI_REG8(0x317c)
#define IMX290_ADBIT2_10BIT 0x12
#define IMX290_ADBIT2_12BIT 0x00
#define IMX290_ADBIT3 CCI_REG8(0x31ec)
#define IMX290_ADBIT3_10BIT 0x37
#define IMX290_ADBIT3_12BIT 0x0e
#define IMX290_REPETITION CCI_REG8(0x3405)
#define IMX290_PHY_LANE_NUM CCI_REG8(0x3407)
#define IMX290_OPB_SIZE_V CCI_REG8(0x3414)
#define IMX290_Y_OUT_SIZE CCI_REG16_LE(0x3418)
#define IMX290_CSI_DT_FMT CCI_REG16_LE(0x3441)
#define IMX290_CSI_DT_FMT_RAW10 0x0a0a
#define IMX290_CSI_DT_FMT_RAW12 0x0c0c
#define IMX290_CSI_LANE_MODE CCI_REG8(0x3443)
#define IMX290_EXTCK_FREQ CCI_REG16_LE(0x3444)
#define IMX290_TCLKPOST CCI_REG16_LE(0x3446)
#define IMX290_THSZERO CCI_REG16_LE(0x3448)
#define IMX290_THSPREPARE CCI_REG16_LE(0x344a)
#define IMX290_TCLKTRAIL CCI_REG16_LE(0x344c)
#define IMX290_THSTRAIL CCI_REG16_LE(0x344e)
#define IMX290_TCLKZERO CCI_REG16_LE(0x3450)
#define IMX290_TCLKPREPARE CCI_REG16_LE(0x3452)
#define IMX290_TLPX CCI_REG16_LE(0x3454)
#define IMX290_X_OUT_SIZE CCI_REG16_LE(0x3472)
#define IMX290_INCKSEL7 CCI_REG8(0x3480)
#define IMX290_PGCTRL_REGEN BIT(0)
#define IMX290_PGCTRL_THRU BIT(1)
#define IMX290_PGCTRL_MODE(n) ((n) << 4)
/* Number of lines by which exposure must be less than VMAX */
#define IMX290_EXPOSURE_OFFSET 2
#define IMX290_PIXEL_RATE 148500000
/*
* The IMX290 pixel array is organized as follows:
*
* +------------------------------------+
* | Optical Black | } Vertical effective optical black (10)
* +---+------------------------------------+---+
* | | | | } Effective top margin (8)
* | | +----------------------------+ | | \
* | | | | | | |
* | | | | | | |
* | | | | | | |
* | | | Recording Pixel Area | | | | Recommended height (1080)
* | | | | | | |
* | | | | | | |
* | | | | | | |
* | | +----------------------------+ | | /
* | | | | } Effective bottom margin (9)
* +---+------------------------------------+---+
* <-> <-> <--------------------------> <-> <->
* \---- Ignored right margin (4)
* \-------- Effective right margin (9)
* \------------------------- Recommended width (1920)
* \----------------------------------------- Effective left margin (8)
* \--------------------------------------------- Ignored left margin (4)
*
* The optical black lines are output over CSI-2 with a separate data type.
*
* The pixel array is meant to have 1920x1080 usable pixels after image
* processing in an ISP. It has 8 (9) extra active pixels usable for color
* processing in the ISP on the top and left (bottom and right) sides of the
* image. In addition, 4 additional pixels are present on the left and right
* sides of the image, documented as "ignored area".
*
* As far as is understood, all pixels of the pixel array (ignored area, color
* processing margins and recording area) can be output by the sensor.
*/
#define IMX290_PIXEL_ARRAY_WIDTH 1945
#define IMX290_PIXEL_ARRAY_HEIGHT 1097
#define IMX290_PIXEL_ARRAY_MARGIN_LEFT 12
#define IMX290_PIXEL_ARRAY_MARGIN_RIGHT 13
#define IMX290_PIXEL_ARRAY_MARGIN_TOP 8
#define IMX290_PIXEL_ARRAY_MARGIN_BOTTOM 9
#define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920
#define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080
/* Equivalent value for 16bpp */
#define IMX290_BLACK_LEVEL_DEFAULT 3840
#define IMX290_NUM_SUPPLIES 3
enum imx290_colour_variant {
IMX290_VARIANT_COLOUR,
IMX290_VARIANT_MONO,
IMX290_VARIANT_MAX
};
enum imx290_model {
IMX290_MODEL_IMX290LQR,
IMX290_MODEL_IMX290LLR,
IMX290_MODEL_IMX327LQR,
IMX290_MODEL_IMX462LQR,
IMX290_MODEL_IMX462LLR,
};
struct imx290_model_info {
enum imx290_colour_variant colour_variant;
const struct cci_reg_sequence *init_regs;
size_t init_regs_num;
unsigned int max_analog_gain;
const char *name;
};
enum imx290_clk_freq {
IMX290_CLK_37_125,
IMX290_CLK_74_25,
IMX290_NUM_CLK
};
/*
* Clock configuration for registers INCKSEL1 to INCKSEL6.
*/
struct imx290_clk_cfg {
u8 incksel1;
u8 incksel2;
u8 incksel3;
u8 incksel4;
u8 incksel5;
u8 incksel6;
};
struct imx290_mode {
u32 width;
u32 height;
u32 hmax_min;
u32 vmax_min;
u8 link_freq_index;
u8 ctrl_07;
const struct cci_reg_sequence *data;
u32 data_size;
const struct imx290_clk_cfg *clk_cfg;
};
struct imx290_csi_cfg {
u16 repetition;
u16 tclkpost;
u16 thszero;
u16 thsprepare;
u16 tclktrail;
u16 thstrail;
u16 tclkzero;
u16 tclkprepare;
u16 tlpx;
};
struct imx290 {
struct device *dev;
struct clk *xclk;
struct regmap *regmap;
enum imx290_clk_freq xclk_idx;
u8 nlanes;
const struct imx290_model_info *model;
struct v4l2_subdev sd;
struct media_pad pad;
const struct imx290_mode *current_mode;
struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
struct gpio_desc *rst_gpio;
struct v4l2_ctrl_handler ctrls;
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *hblank;
struct v4l2_ctrl *vblank;
struct v4l2_ctrl *exposure;
struct {
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vflip;
};
};
static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
{
return container_of(_sd, struct imx290, sd);
}
/* -----------------------------------------------------------------------------
* Modes and formats
*/
static const struct cci_reg_sequence imx290_global_init_settings[] = {
{ IMX290_WINWV_OB, 12 },
{ IMX290_WINPH, 0 },
{ IMX290_WINPV, 0 },
{ IMX290_WINWH, 1948 },
{ IMX290_WINWV, 1097 },
{ IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
{ CCI_REG8(0x3012), 0x64 },
{ CCI_REG8(0x3013), 0x00 },
};
static const struct cci_reg_sequence imx290_global_init_settings_290[] = {
{ CCI_REG8(0x300f), 0x00 },
{ CCI_REG8(0x3010), 0x21 },
{ CCI_REG8(0x3011), 0x00 },
{ CCI_REG8(0x3016), 0x09 },
{ CCI_REG8(0x3070), 0x02 },
{ CCI_REG8(0x3071), 0x11 },
{ CCI_REG8(0x309b), 0x10 },
{ CCI_REG8(0x309c), 0x22 },
{ CCI_REG8(0x30a2), 0x02 },
{ CCI_REG8(0x30a6), 0x20 },
{ CCI_REG8(0x30a8), 0x20 },
{ CCI_REG8(0x30aa), 0x20 },
{ CCI_REG8(0x30ac), 0x20 },
{ CCI_REG8(0x30b0), 0x43 },
{ CCI_REG8(0x3119), 0x9e },
{ CCI_REG8(0x311c), 0x1e },
{ CCI_REG8(0x311e), 0x08 },
{ CCI_REG8(0x3128), 0x05 },
{ CCI_REG8(0x313d), 0x83 },
{ CCI_REG8(0x3150), 0x03 },
{ CCI_REG8(0x317e), 0x00 },
{ CCI_REG8(0x32b8), 0x50 },
{ CCI_REG8(0x32b9), 0x10 },
{ CCI_REG8(0x32ba), 0x00 },
{ CCI_REG8(0x32bb), 0x04 },
{ CCI_REG8(0x32c8), 0x50 },
{ CCI_REG8(0x32c9), 0x10 },
{ CCI_REG8(0x32ca), 0x00 },
{ CCI_REG8(0x32cb), 0x04 },
{ CCI_REG8(0x332c), 0xd3 },
{ CCI_REG8(0x332d), 0x10 },
{ CCI_REG8(0x332e), 0x0d },
{ CCI_REG8(0x3358), 0x06 },
{ CCI_REG8(0x3359), 0xe1 },
{ CCI_REG8(0x335a), 0x11 },
{ CCI_REG8(0x3360), 0x1e },
{ CCI_REG8(0x3361), 0x61 },
{ CCI_REG8(0x3362), 0x10 },
{ CCI_REG8(0x33b0), 0x50 },
{ CCI_REG8(0x33b2), 0x1a },
{ CCI_REG8(0x33b3), 0x04 },
};
static const struct cci_reg_sequence imx290_global_init_settings_462[] = {
{ CCI_REG8(0x300f), 0x00 },
{ CCI_REG8(0x3010), 0x21 },
{ CCI_REG8(0x3011), 0x02 },
{ CCI_REG8(0x3016), 0x09 },
{ CCI_REG8(0x3070), 0x02 },
{ CCI_REG8(0x3071), 0x11 },
{ CCI_REG8(0x309b), 0x10 },
{ CCI_REG8(0x309c), 0x22 },
{ CCI_REG8(0x30a2), 0x02 },
{ CCI_REG8(0x30a6), 0x20 },
{ CCI_REG8(0x30a8), 0x20 },
{ CCI_REG8(0x30aa), 0x20 },
{ CCI_REG8(0x30ac), 0x20 },
{ CCI_REG8(0x30b0), 0x43 },
{ CCI_REG8(0x3119), 0x9e },
{ CCI_REG8(0x311c), 0x1e },
{ CCI_REG8(0x311e), 0x08 },
{ CCI_REG8(0x3128), 0x05 },
{ CCI_REG8(0x313d), 0x83 },
{ CCI_REG8(0x3150), 0x03 },
{ CCI_REG8(0x317e), 0x00 },
{ CCI_REG8(0x32b8), 0x50 },
{ CCI_REG8(0x32b9), 0x10 },
{ CCI_REG8(0x32ba), 0x00 },
{ CCI_REG8(0x32bb), 0x04 },
{ CCI_REG8(0x32c8), 0x50 },
{ CCI_REG8(0x32c9), 0x10 },
{ CCI_REG8(0x32ca), 0x00 },
{ CCI_REG8(0x32cb), 0x04 },
{ CCI_REG8(0x332c), 0xd3 },
{ CCI_REG8(0x332d), 0x10 },
{ CCI_REG8(0x332e), 0x0d },
{ CCI_REG8(0x3358), 0x06 },
{ CCI_REG8(0x3359), 0xe1 },
{ CCI_REG8(0x335a), 0x11 },
{ CCI_REG8(0x3360), 0x1e },
{ CCI_REG8(0x3361), 0x61 },
{ CCI_REG8(0x3362), 0x10 },
{ CCI_REG8(0x33b0), 0x50 },
{ CCI_REG8(0x33b2), 0x1a },
{ CCI_REG8(0x33b3), 0x04 },
};
#define IMX290_NUM_CLK_REGS 2
static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = {
[IMX290_CLK_37_125] = {
{ IMX290_EXTCK_FREQ, (37125 * 256) / 1000 },
{ IMX290_INCKSEL7, 0x49 },
},
[IMX290_CLK_74_25] = {
{ IMX290_EXTCK_FREQ, (74250 * 256) / 1000 },
{ IMX290_INCKSEL7, 0x92 },
},
};
static const struct cci_reg_sequence imx290_global_init_settings_327[] = {
{ CCI_REG8(0x3011), 0x02 },
{ CCI_REG8(0x309e), 0x4A },
{ CCI_REG8(0x309f), 0x4A },
{ CCI_REG8(0x313b), 0x61 },
};
static const struct cci_reg_sequence imx290_1080p_settings[] = {
/* mode settings */
{ IMX290_WINWV_OB, 12 },
{ IMX290_OPB_SIZE_V, 10 },
{ IMX290_X_OUT_SIZE, 1920 },
{ IMX290_Y_OUT_SIZE, 1080 },
};
static const struct cci_reg_sequence imx290_720p_settings[] = {
/* mode settings */
{ IMX290_WINWV_OB, 6 },
{ IMX290_OPB_SIZE_V, 4 },
{ IMX290_X_OUT_SIZE, 1280 },
{ IMX290_Y_OUT_SIZE, 720 },
};
static const struct cci_reg_sequence imx290_10bit_settings[] = {
{ IMX290_ADBIT, IMX290_ADBIT_10BIT },
{ IMX290_OUT_CTRL, IMX290_ODBIT_10BIT },
{ IMX290_ADBIT1, IMX290_ADBIT1_10BIT },
{ IMX290_ADBIT2, IMX290_ADBIT2_10BIT },
{ IMX290_ADBIT3, IMX290_ADBIT3_10BIT },
{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 },
};
static const struct cci_reg_sequence imx290_12bit_settings[] = {
{ IMX290_ADBIT, IMX290_ADBIT_12BIT },
{ IMX290_OUT_CTRL, IMX290_ODBIT_12BIT },
{ IMX290_ADBIT1, IMX290_ADBIT1_12BIT },
{ IMX290_ADBIT2, IMX290_ADBIT2_12BIT },
{ IMX290_ADBIT3, IMX290_ADBIT3_12BIT },
{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 },
};
static const struct imx290_csi_cfg imx290_csi_222_75mhz = {
/* 222.75MHz or 445.5Mbit/s per lane */
.repetition = 0x10,
.tclkpost = 87,
.thszero = 55,
.thsprepare = 31,
.tclktrail = 31,
.thstrail = 31,
.tclkzero = 119,
.tclkprepare = 31,
.tlpx = 23,
};
static const struct imx290_csi_cfg imx290_csi_445_5mhz = {
/* 445.5MHz or 891Mbit/s per lane */
.repetition = 0x00,
.tclkpost = 119,
.thszero = 103,
.thsprepare = 71,
.tclktrail = 55,
.thstrail = 63,
.tclkzero = 255,
.tclkprepare = 63,
.tlpx = 55,
};
static const struct imx290_csi_cfg imx290_csi_148_5mhz = {
/* 148.5MHz or 297Mbit/s per lane */
.repetition = 0x10,
.tclkpost = 79,
.thszero = 47,
.thsprepare = 23,
.tclktrail = 23,
.thstrail = 23,
.tclkzero = 87,
.tclkprepare = 23,
.tlpx = 23,
};
static const struct imx290_csi_cfg imx290_csi_297mhz = {
/* 297MHz or 594Mbit/s per lane */
.repetition = 0x00,
.tclkpost = 103,
.thszero = 87,
.thsprepare = 47,
.tclktrail = 39,
.thstrail = 47,
.tclkzero = 191,
.tclkprepare = 47,
.tlpx = 39,
};
/* supported link frequencies */
#define FREQ_INDEX_1080P 0
#define FREQ_INDEX_720P 1
static const s64 imx290_link_freq_2lanes[] = {
[FREQ_INDEX_1080P] = 445500000,
[FREQ_INDEX_720P] = 297000000,
};
static const s64 imx290_link_freq_4lanes[] = {
[FREQ_INDEX_1080P] = 222750000,
[FREQ_INDEX_720P] = 148500000,
};
/*
* In this function and in the similar ones below We rely on imx290_probe()
* to ensure that nlanes is either 2 or 4.
*/
static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
{
if (imx290->nlanes == 2)
return imx290_link_freq_2lanes;
else
return imx290_link_freq_4lanes;
}
static inline int imx290_link_freqs_num(const struct imx290 *imx290)
{
if (imx290->nlanes == 2)
return ARRAY_SIZE(imx290_link_freq_2lanes);
else
return ARRAY_SIZE(imx290_link_freq_4lanes);
}
static const struct imx290_clk_cfg imx290_1080p_clock_config[] = {
[IMX290_CLK_37_125] = {
/* 37.125MHz clock config */
.incksel1 = 0x18,
.incksel2 = 0x03,
.incksel3 = 0x20,
.incksel4 = 0x01,
.incksel5 = 0x1a,
.incksel6 = 0x1a,
},
[IMX290_CLK_74_25] = {
/* 74.25MHz clock config */
.incksel1 = 0x0c,
.incksel2 = 0x03,
.incksel3 = 0x10,
.incksel4 = 0x01,
.incksel5 = 0x1b,
.incksel6 = 0x1b,
},
};
static const struct imx290_clk_cfg imx290_720p_clock_config[] = {
[IMX290_CLK_37_125] = {
/* 37.125MHz clock config */
.incksel1 = 0x20,
.incksel2 = 0x00,
.incksel3 = 0x20,
.incksel4 = 0x01,
.incksel5 = 0x1a,
.incksel6 = 0x1a,
},
[IMX290_CLK_74_25] = {
/* 74.25MHz clock config */
.incksel1 = 0x10,
.incksel2 = 0x00,
.incksel3 = 0x10,
.incksel4 = 0x01,
.incksel5 = 0x1b,
.incksel6 = 0x1b,
},
};
/* Mode configs */
static const struct imx290_mode imx290_modes_2lanes[] = {
{
.width = 1920,
.height = 1080,
.hmax_min = 2200,
.vmax_min = 1125,
.link_freq_index = FREQ_INDEX_1080P,
.ctrl_07 = IMX290_WINMODE_1080P,
.data = imx290_1080p_settings,
.data_size = ARRAY_SIZE(imx290_1080p_settings),
.clk_cfg = imx290_1080p_clock_config,
},
{
.width = 1280,
.height = 720,
.hmax_min = 3300,
.vmax_min = 750,
.link_freq_index = FREQ_INDEX_720P,
.ctrl_07 = IMX290_WINMODE_720P,
.data = imx290_720p_settings,
.data_size = ARRAY_SIZE(imx290_720p_settings),
.clk_cfg = imx290_720p_clock_config,
},
};
static const struct imx290_mode imx290_modes_4lanes[] = {
{
.width = 1920,
.height = 1080,
.hmax_min = 2200,
.vmax_min = 1125,
.link_freq_index = FREQ_INDEX_1080P,
.ctrl_07 = IMX290_WINMODE_1080P,
.data = imx290_1080p_settings,
.data_size = ARRAY_SIZE(imx290_1080p_settings),
.clk_cfg = imx290_1080p_clock_config,
},
{
.width = 1280,
.height = 720,
.hmax_min = 3300,
.vmax_min = 750,
.link_freq_index = FREQ_INDEX_720P,
.ctrl_07 = IMX290_WINMODE_720P,
.data = imx290_720p_settings,
.data_size = ARRAY_SIZE(imx290_720p_settings),
.clk_cfg = imx290_720p_clock_config,
},
};
static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
{
if (imx290->nlanes == 2)
return imx290_modes_2lanes;
else
return imx290_modes_4lanes;
}
static inline int imx290_modes_num(const struct imx290 *imx290)
{
if (imx290->nlanes == 2)
return ARRAY_SIZE(imx290_modes_2lanes);
else
return ARRAY_SIZE(imx290_modes_4lanes);
}
struct imx290_format_info {
u32 code[IMX290_VARIANT_MAX];
u8 bpp;
const struct cci_reg_sequence *regs;
unsigned int num_regs;
};
static const struct imx290_format_info imx290_formats[] = {
{
.code = {
[IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10,
[IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10
},
.bpp = 10,
.regs = imx290_10bit_settings,
.num_regs = ARRAY_SIZE(imx290_10bit_settings),
}, {
.code = {
[IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12,
[IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12
},
.bpp = 12,
.regs = imx290_12bit_settings,
.num_regs = ARRAY_SIZE(imx290_12bit_settings),
}
};
static const struct imx290_format_info *
imx290_format_info(const struct imx290 *imx290, u32 code)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) {
const struct imx290_format_info *info = &imx290_formats[i];
if (info->code[imx290->model->colour_variant] == code)
return info;
}
return NULL;
}
static int imx290_set_register_array(struct imx290 *imx290,
const struct cci_reg_sequence *settings,
unsigned int num_settings)
{
int ret;
ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL);
if (ret < 0)
return ret;
/* Provide 10ms settle time */
usleep_range(10000, 11000);
return 0;
}
static int imx290_set_clock(struct imx290 *imx290)
{
const struct imx290_mode *mode = imx290->current_mode;
enum imx290_clk_freq clk_idx = imx290->xclk_idx;
const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx];
int ret;
ret = imx290_set_register_array(imx290, xclk_regs[clk_idx],
IMX290_NUM_CLK_REGS);
cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret);
cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret);
cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret);
cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret);
cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret);
cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret);
return ret;
}
static int imx290_set_data_lanes(struct imx290 *imx290)
{
int ret = 0;
cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1,
&ret);
cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1,
&ret);
cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret);
return ret;
}
static int imx290_set_black_level(struct imx290 *imx290,
const struct v4l2_mbus_framefmt *format,
unsigned int black_level, int *err)
{
unsigned int bpp = imx290_format_info(imx290, format->code)->bpp;
return cci_write(imx290->regmap, IMX290_BLKLEVEL,
black_level >> (16 - bpp), err);
}
static int imx290_set_csi_config(struct imx290 *imx290)
{
const s64 *link_freqs = imx290_link_freqs_ptr(imx290);
const struct imx290_csi_cfg *csi_cfg;
int ret = 0;
switch (link_freqs[imx290->current_mode->link_freq_index]) {
case 445500000:
csi_cfg = &imx290_csi_445_5mhz;
break;
case 297000000:
csi_cfg = &imx290_csi_297mhz;
break;
case 222750000:
csi_cfg = &imx290_csi_222_75mhz;
break;
case 148500000:
csi_cfg = &imx290_csi_148_5mhz;
break;
default:
return -EINVAL;
}
cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret);
cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret);
cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret);
cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret);
cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret);
cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret);
cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret);
cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare,
&ret);
cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret);
return ret;
}
static int imx290_setup_format(struct imx290 *imx290,
const struct v4l2_mbus_framefmt *format)
{
const struct imx290_format_info *info;
int ret;
info = imx290_format_info(imx290, format->code);
ret = imx290_set_register_array(imx290, info->regs, info->num_regs);
if (ret < 0) {
dev_err(imx290->dev, "Could not set format registers\n");
return ret;
}
return imx290_set_black_level(imx290, format,
IMX290_BLACK_LEVEL_DEFAULT, &ret);
}
/* ----------------------------------------------------------------------------
* Controls
*/
static void imx290_exposure_update(struct imx290 *imx290,
const struct imx290_mode *mode)
{
unsigned int exposure_max;
exposure_max = imx290->vblank->val + mode->height -
IMX290_EXPOSURE_OFFSET;
__v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1,
exposure_max);
}
static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct imx290 *imx290 = container_of(ctrl->handler,
struct imx290, ctrls);
const struct v4l2_mbus_framefmt *format;
struct v4l2_subdev_state *state;
int ret = 0, vmax;
/*
* Return immediately for controls that don't need to be applied to the
* device.
*/
if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)
return 0;
if (ctrl->id == V4L2_CID_VBLANK) {
/* Changing vblank changes the allowed range for exposure. */
imx290_exposure_update(imx290, imx290->current_mode);
}
/* V4L2 controls values will be applied only when power is already up */
if (!pm_runtime_get_if_in_use(imx290->dev))
return 0;
state = v4l2_subdev_get_locked_active_state(&imx290->sd);
format = v4l2_subdev_state_get_format(state, 0);
switch (ctrl->id) {
case V4L2_CID_ANALOGUE_GAIN:
ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL);
break;
case V4L2_CID_VBLANK:
ret = cci_write(imx290->regmap, IMX290_VMAX,
ctrl->val + imx290->current_mode->height, NULL);
/*
* Due to the way that exposure is programmed in this sensor in
* relation to VMAX, we have to reprogramme it whenever VMAX is
* changed.
* Update ctrl so that the V4L2_CID_EXPOSURE case can refer to
* it.
*/
ctrl = imx290->exposure;
fallthrough;
case V4L2_CID_EXPOSURE:
vmax = imx290->vblank->val + imx290->current_mode->height;
ret = cci_write(imx290->regmap, IMX290_SHS1,
vmax - ctrl->val - 1, NULL);
break;
case V4L2_CID_TEST_PATTERN:
if (ctrl->val) {
imx290_set_black_level(imx290, format, 0, &ret);
usleep_range(10000, 11000);
cci_write(imx290->regmap, IMX290_PGCTRL,
(u8)(IMX290_PGCTRL_REGEN |
IMX290_PGCTRL_THRU |
IMX290_PGCTRL_MODE(ctrl->val)), &ret);
} else {
cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret);
usleep_range(10000, 11000);
imx290_set_black_level(imx290, format,
IMX290_BLACK_LEVEL_DEFAULT, &ret);
}
break;
case V4L2_CID_HBLANK:
ret = cci_write(imx290->regmap, IMX290_HMAX,
ctrl->val + imx290->current_mode->width, NULL);
break;
case V4L2_CID_HFLIP:
case V4L2_CID_VFLIP:
{
u32 reg;
reg = imx290->current_mode->ctrl_07;
if (imx290->hflip->val)
reg |= IMX290_HREVERSE;
if (imx290->vflip->val)
reg |= IMX290_VREVERSE;
ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL);
break;
}
default:
ret = -EINVAL;
break;
}
pm_runtime_mark_last_busy(imx290->dev);
pm_runtime_put_autosuspend(imx290->dev);
return ret;
}
static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
.s_ctrl = imx290_set_ctrl,
};
static const char * const imx290_test_pattern_menu[] = {
"Disabled",
"Sequence Pattern 1",
"Horizontal Color-bar Chart",
"Vertical Color-bar Chart",
"Sequence Pattern 2",
"Gradation Pattern 1",
"Gradation Pattern 2",
"000/555h Toggle Pattern",
};
static void imx290_ctrl_update(struct imx290 *imx290,
const struct imx290_mode *mode)
{
unsigned int hblank_min = mode->hmax_min - mode->width;
unsigned int hblank_max = IMX290_HMAX_MAX - mode->width;
unsigned int vblank_min = mode->vmax_min - mode->height;
unsigned int vblank_max = IMX290_VMAX_MAX - mode->height;
__v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index);
__v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1,
hblank_min);
__v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1,
vblank_min);
}
static int imx290_ctrl_init(struct imx290 *imx290)
{
struct v4l2_fwnode_device_properties props;
int ret;
ret = v4l2_fwnode_device_parse(imx290->dev, &props);
if (ret < 0)
return ret;
v4l2_ctrl_handler_init(&imx290->ctrls, 11);
/*
* The sensor has an analog gain and a digital gain, both controlled
* through a single gain value, expressed in 0.3dB increments. Values
* from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values
* up to 72.0dB (240) add further digital gain. Limit the range to
* analog gain only, support for digital gain can be added separately
* if needed.
*/
v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN, 0,
imx290->model->max_analog_gain, 1, 0);
/*
* Correct range will be determined through imx290_ctrl_update setting
* V4L2_CID_VBLANK.
*/
imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_EXPOSURE, 1, 65535, 1,
65535);
/*
* Set the link frequency, pixel rate, horizontal blanking and vertical
* blanking to hardcoded values, they will be updated by
* imx290_ctrl_update().
*/
imx290->link_freq =
v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_LINK_FREQ,
imx290_link_freqs_num(imx290) - 1, 0,
imx290_link_freqs_ptr(imx290));
if (imx290->link_freq)
imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE,
IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1,
IMX290_PIXEL_RATE);
v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(imx290_test_pattern_menu) - 1,
0, 0, imx290_test_pattern_menu);
/*
* Actual range will be set from imx290_ctrl_update later in the probe.
*/
imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_HBLANK, 1, 1, 1, 1);
imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_VBLANK, 1, 1, 1, 1);
imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_HFLIP, 0, 1, 1, 0);
imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_VFLIP, 0, 1, 1, 0);
v4l2_ctrl_cluster(2, &imx290->hflip);
v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops,
&props);
imx290->sd.ctrl_handler = &imx290->ctrls;
if (imx290->ctrls.error) {
ret = imx290->ctrls.error;
v4l2_ctrl_handler_free(&imx290->ctrls);
return ret;
}
return 0;
}
/* ----------------------------------------------------------------------------
* Subdev operations
*/
/* Start streaming */
static int imx290_start_streaming(struct imx290 *imx290,
struct v4l2_subdev_state *state)
{
const struct v4l2_mbus_framefmt *format;
int ret;