SOMADOR_4BIT.txt

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY work;
USE work.ALL;

entity SOMADOR is port(
						A  : in STD_LOGIC_VECTOR(7 DOWNTO 0);
						B  : in STD_LOGIC_VECTOR(7 DOWNTO 0);
						S0 : out STD_LOGIC_VECTOR(7 DOWNTO 0);
						S1 : out STD_LOGIC);
end SOMADOR;

architecture estrutural of SOMADOR is

component SOMADOR_COMPLETO is Port( A  : in STD_LOGIC;
								    B  : in STD_LOGIC;
								    C  : in STD_LOGIC;
								    S0 : out STD_LOGIC;
								    S1 : out STD_LOGIC);
end component;
 
signal AUX : STD_LOGIC_VECTOR(6 DOWNTO 0);

begin

	somador0: SOMADOR_COMPLETO port map (A(0), B(0), '0', S0(0), AUX(0));
	somador1: SOMADOR_COMPLETO port map (A(1), B(1), AUX(0), S0(1), AUX(1));  
	somador2: SOMADOR_COMPLETO port map (A(2), B(2), AUX(1), S0(2), AUX(2));
	somador3: SOMADOR_COMPLETO port map (A(3), B(3), AUX(2), S0(3), AUX(3));
	somador4: SOMADOR_COMPLETO port map (A(4), B(4), AUX(3), S0(4), AUX(4));
	somador5: SOMADOR_COMPLETO port map (A(5), B(5), AUX(4), S0(5), AUX(5));
	somador6: SOMADOR_COMPLETO port map (A(6), B(6), AUX(5), S0(6), AUX(6));
	somador7: SOMADOR_COMPLETO port map (A(7), B(7), AUX(6), S0(7), S1);


end estrutural;