Ventus GPGPU(Verilog Edition)

GPGPU processor supporting RISCV-V extension, developed with Verilog.

Copyright (c) 2023-2024 C*Core Technology Co.,Ltd,Suzhou.

这是“乘影”的Verilog版本，原版（Chisel HDL）链接在这里

乘影开源GPGPU项目网站：opengpgpu.org.cn

目前乘影在硬件设计上还有很多不足，如果您有意愿参与到“乘影”的开发中，欢迎在github上pull request

Architecture

乘影的硬件架构文档在这里

承影的硬件结构框图如下所示:

SM核的硬件结构框图如下所示:

Getting started

以gassian用例为例，进入testcase/test_gpgpu_axi_top/tc_gaussian:

• 打开tc.v,选择case的warp数和thread数

在modules/define/define.v目录下，修改NUM_THREAD，可以更改warp内的thread数量

• 用VCS仿真:

make run-vcs

• 结果会显示passed或failed

• 用Verdi查看波形

make verdi

• 如果不需要对外的AXI接口，则进入testcase/test_gpgpu_top/tc_gaussian，步骤同上

Case Description

Acknowledgement

We refer to some open-source design when developing Ventus GPGPU.

Sub module	Source	Detail
CTA scheduler	MIAOW	Our CTA scheduler module is based on MiaoW ultra-threads dispatcher
L2Cache	block-inclusivecache-sifive	Our L2Cache design is inspired by Sifive's block-inclusivecache
FPU	XiangShan	We reused Array Multiplier in XiangShan. FPU design is also inspired by XiangShan
SFU	openhwgroup	Our SFU module is based on pulp-platform
Config, ...	rocket-chip	Some modules are sourced from RocketChip