IC design and development should be faster，simpler and more reliable

RTL, Cmodel, and testbench for NVDLA

The Ultra-Low Power RISC-V Core

OpenXuantie - OpenC910 Core

中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程

Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.