RapidWright 2018.2.0-beta Release

Notes:

• Initial release with new RapidWright API Library
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.
• Issue #4 - JDK9 Compliance for some 3rd party libraries prints out warnings