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NDS.cpp
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NDS.cpp
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/*
Copyright 2016-2021 Arisotura
This file is part of melonDS.
melonDS is free software: you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option)
any later version.
melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with melonDS. If not, see http://www.gnu.org/licenses/.
*/
#include <stdio.h>
#include <string.h>
#include "Config.h"
#include "NDS.h"
#include "ARM.h"
#include "NDSCart.h"
#include "GBACart.h"
#include "DMA.h"
#include "FIFO.h"
#include "GPU.h"
#include "SPU.h"
#include "SPI.h"
#include "RTC.h"
#include "Wifi.h"
#include "AREngine.h"
#include "Platform.h"
#include "NDSCart_SRAMManager.h"
#ifdef JIT_ENABLED
#include "ARMJIT.h"
#include "ARMJIT_Memory.h"
#endif
#include "DSi.h"
#include "DSi_SPI_TSC.h"
namespace NDS
{
// timing notes
//
// * this implementation is technically wrong for VRAM
// each bank is considered a separate region
// but this would only matter in specific VRAM->VRAM DMA transfers or
// when running code in VRAM, which is way unlikely
//
// bus/basedelay/nspenalty
//
// bus types:
// * 0 / 32-bit: nothing special
// * 1 / 16-bit: 32-bit accesses split into two 16-bit accesses, second is always sequential
// * 2 / 8-bit/GBARAM: (presumably) split into multiple 8-bit accesses?
// * 3 / ARM9 internal: cache/TCM
//
// ARM9 always gets 3c nonseq penalty when using the bus (except for mainRAM where the penalty is 7c)
// /!\ 3c penalty doesn't apply to DMA!
//
// ARM7 only gets nonseq penalty when accessing mainRAM (7c as for ARM9)
//
// timings for GBA slot and wifi are set up at runtime
int ConsoleType;
u8 ARM9MemTimings[0x40000][4];
u8 ARM7MemTimings[0x20000][4];
ARMv5* ARM9;
ARMv4* ARM7;
u32 NumFrames;
u32 NumLagFrames;
bool LagFrameFlag;
u64 LastSysClockCycles;
u64 FrameStartTimestamp;
int CurCPU;
const s32 kMaxIterationCycles = 64;
u32 ARM9ClockShift;
// no need to worry about those overflowing, they can keep going for atleast 4350 years
u64 ARM9Timestamp, ARM9Target;
u64 ARM7Timestamp, ARM7Target;
u64 SysTimestamp;
SchedEvent SchedList[Event_MAX];
u32 SchedListMask;
u32 CPUStop;
u8 ARM9BIOS[0x1000];
u8 ARM7BIOS[0x4000];
u8* MainRAM;
u32 MainRAMMask;
u8* SharedWRAM;
u8 WRAMCnt;
// putting them together so they're always next to each other
MemRegion SWRAM_ARM9;
MemRegion SWRAM_ARM7;
u8* ARM7WRAM;
u16 ExMemCnt[2];
// TODO: these belong in NDSCart!
u8 ROMSeed0[2*8];
u8 ROMSeed1[2*8];
// IO shit
u32 IME[2];
u32 IE[2], IF[2];
u32 IE2, IF2;
u8 PostFlag9;
u8 PostFlag7;
u16 PowerControl9;
u16 PowerControl7;
u16 WifiWaitCnt;
u16 ARM7BIOSProt;
Timer Timers[8];
u8 TimerCheckMask[2];
u64 TimerTimestamp[2];
DMA* DMAs[8];
u32 DMA9Fill[4];
u16 IPCSync9, IPCSync7;
u16 IPCFIFOCnt9, IPCFIFOCnt7;
FIFO<u32, 16> IPCFIFO9; // FIFO in which the ARM9 writes
FIFO<u32, 16> IPCFIFO7;
u16 DivCnt;
u32 DivNumerator[2];
u32 DivDenominator[2];
u32 DivQuotient[2];
u32 DivRemainder[2];
u16 SqrtCnt;
u32 SqrtVal[2];
u32 SqrtRes;
u32 KeyInput;
u16 KeyCnt;
u16 RCnt;
bool Running;
bool RunningGame;
void DivDone(u32 param);
void SqrtDone(u32 param);
void RunTimer(u32 tid, s32 cycles);
void SetWifiWaitCnt(u16 val);
void SetGBASlotTimings();
bool Init()
{
ARM9 = new ARMv5();
ARM7 = new ARMv4();
#ifdef JIT_ENABLED
ARMJIT::Init();
#else
MainRAM = new u8[0x1000000];
ARM7WRAM = new u8[ARM7WRAMSize];
SharedWRAM = new u8[SharedWRAMSize];
#endif
DMAs[0] = new DMA(0, 0);
DMAs[1] = new DMA(0, 1);
DMAs[2] = new DMA(0, 2);
DMAs[3] = new DMA(0, 3);
DMAs[4] = new DMA(1, 0);
DMAs[5] = new DMA(1, 1);
DMAs[6] = new DMA(1, 2);
DMAs[7] = new DMA(1, 3);
if (!NDSCart_SRAMManager::Init()) return false;
if (!NDSCart::Init()) return false;
if (!GBACart::Init()) return false;
if (!GPU::Init()) return false;
if (!SPU::Init()) return false;
if (!SPI::Init()) return false;
if (!RTC::Init()) return false;
if (!Wifi::Init()) return false;
if (!DSi::Init()) return false;
if (!AREngine::Init()) return false;
return true;
}
void DeInit()
{
#ifdef JIT_ENABLED
ARMJIT::DeInit();
#endif
delete ARM9;
delete ARM7;
for (int i = 0; i < 8; i++)
delete DMAs[i];
NDSCart_SRAMManager::DeInit();
NDSCart::DeInit();
GBACart::DeInit();
GPU::DeInit();
SPU::DeInit();
SPI::DeInit();
RTC::DeInit();
Wifi::DeInit();
DSi::DeInit();
AREngine::DeInit();
}
void SetARM9RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, int seq)
{
addrstart >>= 14;
addrend >>= 14;
if (addrend == 0x3FFFF) addrend++;
int N16, S16, N32, S32;
N16 = nonseq;
S16 = seq;
if (buswidth == 16)
{
N32 = N16 + S16;
S32 = S16 + S16;
}
else
{
N32 = N16;
S32 = S16;
}
for (u32 i = addrstart; i < addrend; i++)
{
ARM9MemTimings[i][0] = N16;
ARM9MemTimings[i][1] = S16;
ARM9MemTimings[i][2] = N32;
ARM9MemTimings[i][3] = S32;
}
ARM9->UpdateRegionTimings(addrstart<<14, addrend == 0x40000
? 0xFFFFFFFF
: (addrend<<14));
}
void SetARM7RegionTimings(u32 addrstart, u32 addrend, int buswidth, int nonseq, int seq)
{
addrstart >>= 15;
addrend >>= 15;
if (addrend == 0x1FFFF) addrend++;
int N16, S16, N32, S32;
N16 = nonseq;
S16 = seq;
if (buswidth == 16)
{
N32 = N16 + S16;
S32 = S16 + S16;
}
else
{
N32 = N16;
S32 = S16;
}
for (u32 i = addrstart; i < addrend; i++)
{
ARM7MemTimings[i][0] = N16;
ARM7MemTimings[i][1] = S16;
ARM7MemTimings[i][2] = N32;
ARM7MemTimings[i][3] = S32;
}
}
void InitTimings()
{
// TODO, eventually:
// VRAM is initially unmapped. The timings should be those of void regions.
// Similarly for any unmapped VRAM area.
// Need to check whether supporting these timing characteristics would impact performance
// (especially wrt VRAM mirroring and overlapping and whatnot).
// ARM9
// TODO: +3c nonseq waitstate doesn't apply to DMA!
// but of course mainRAM always gets 8c nonseq waitstate
// TODO: DSi-specific timings!!
SetARM9RegionTimings(0x00000000, 0xFFFFFFFF, 32, 1 + 3, 1); // void
SetARM9RegionTimings(0xFFFF0000, 0xFFFFFFFF, 32, 1 + 3, 1); // BIOS
SetARM9RegionTimings(0x02000000, 0x03000000, 16, 8, 1); // main RAM
SetARM9RegionTimings(0x03000000, 0x04000000, 32, 1 + 3, 1); // ARM9/shared WRAM
SetARM9RegionTimings(0x04000000, 0x05000000, 32, 1 + 3, 1); // IO
SetARM9RegionTimings(0x05000000, 0x06000000, 16, 1 + 3, 1); // palette
SetARM9RegionTimings(0x06000000, 0x07000000, 16, 1 + 3, 1); // VRAM
SetARM9RegionTimings(0x07000000, 0x08000000, 32, 1 + 3, 1); // OAM
// ARM7
SetARM7RegionTimings(0x00000000, 0xFFFFFFFF, 32, 1, 1); // void
SetARM7RegionTimings(0x00000000, 0x00010000, 32, 1, 1); // BIOS
SetARM7RegionTimings(0x02000000, 0x03000000, 16, 8, 1); // main RAM
SetARM7RegionTimings(0x03000000, 0x04000000, 32, 1, 1); // ARM7/shared WRAM
SetARM7RegionTimings(0x04000000, 0x04800000, 32, 1, 1); // IO
SetARM7RegionTimings(0x06000000, 0x07000000, 16, 1, 1); // ARM7 VRAM
// handled later: GBA slot, wifi
}
void SetupDirectBoot()
{
if (ConsoleType == 1)
{
printf("!! DIRECT BOOT NOT SUPPORTED IN DSI MODE\n");
return;
}
u32 bootparams[8];
memcpy(bootparams, &NDSCart::CartROM[0x20], 8*4);
printf("ARM9: offset=%08X entry=%08X RAM=%08X size=%08X\n",
bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
printf("ARM7: offset=%08X entry=%08X RAM=%08X size=%08X\n",
bootparams[4], bootparams[5], bootparams[6], bootparams[7]);
MapSharedWRAM(3);
u32 arm9start = 0;
// load the ARM9 secure area
if (bootparams[0] >= 0x4000 && bootparams[0] < 0x8000)
{
u8 securearea[0x800];
NDSCart::DecryptSecureArea(securearea);
for (u32 i = 0; i < 0x800; i+=4)
{
ARM9Write32(bootparams[2]+i, *(u32*)&securearea[i]);
arm9start += 4;
}
}
// CHECKME: firmware seems to load this in 0x200 byte chunks
for (u32 i = arm9start; i < bootparams[3]; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[bootparams[0]+i];
ARM9Write32(bootparams[2]+i, tmp);
}
for (u32 i = 0; i < bootparams[7]; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[bootparams[4]+i];
ARM7Write32(bootparams[6]+i, tmp);
}
for (u32 i = 0; i < 0x170; i+=4)
{
u32 tmp = *(u32*)&NDSCart::CartROM[i];
ARM9Write32(0x027FFE00+i, tmp);
}
ARM9Write32(0x027FF800, NDSCart::CartID);
ARM9Write32(0x027FF804, NDSCart::CartID);
ARM9Write16(0x027FF808, *(u16*)&NDSCart::CartROM[0x15E]);
ARM9Write16(0x027FF80A, *(u16*)&NDSCart::CartROM[0x6C]);
ARM9Write16(0x027FF850, 0x5835);
ARM9Write32(0x027FFC00, NDSCart::CartID);
ARM9Write32(0x027FFC04, NDSCart::CartID);
ARM9Write16(0x027FFC08, *(u16*)&NDSCart::CartROM[0x15E]);
ARM9Write16(0x027FFC0A, *(u16*)&NDSCart::CartROM[0x6C]);
ARM9Write16(0x027FFC10, 0x5835);
ARM9Write16(0x027FFC30, 0xFFFF);
ARM9Write16(0x027FFC40, 0x0001);
ARM9->CP15Write(0x910, 0x0300000A);
ARM9->CP15Write(0x911, 0x00000020);
ARM9->CP15Write(0x100, ARM9->CP15Read(0x100) | 0x00050000);
ARM9->R[12] = bootparams[1];
ARM9->R[13] = 0x03002F7C;
ARM9->R[14] = bootparams[1];
ARM9->R_IRQ[0] = 0x03003F80;
ARM9->R_SVC[0] = 0x03003FC0;
ARM7->R[12] = bootparams[5];
ARM7->R[13] = 0x0380FD80;
ARM7->R[14] = bootparams[5];
ARM7->R_IRQ[0] = 0x0380FF80;
ARM7->R_SVC[0] = 0x0380FFC0;
ARM9->JumpTo(bootparams[1]);
ARM7->JumpTo(bootparams[5]);
PostFlag9 = 0x01;
PostFlag7 = 0x01;
PowerControl9 = 0x820F;
GPU::SetPowerCnt(PowerControl9);
// checkme
RCnt = 0x8000;
NDSCart::SPICnt = 0x8000;
SPU::SetBias(0x200);
SetWifiWaitCnt(0x0030);
ARM7BIOSProt = 0x1204;
SPI_Firmware::SetupDirectBoot();
}
void Reset()
{
FILE* f;
u32 i;
RunningGame = false;
LastSysClockCycles = 0;
memset(ARM9BIOS, 0, 0x1000);
memset(ARM7BIOS, 0, 0x4000);
// DS BIOSes are always loaded, even in DSi mode
// we need them for DS-compatible mode
f = Platform::OpenLocalFile(Config::BIOS9Path, "rb");
if (!f)
{
printf("ARM9 BIOS not found\n");
for (i = 0; i < 16; i++)
((u32*)ARM9BIOS)[i] = 0xE7FFDEFF;
}
else
{
fseek(f, 0, SEEK_SET);
fread(ARM9BIOS, 0x1000, 1, f);
printf("ARM9 BIOS loaded\n");
fclose(f);
}
f = Platform::OpenLocalFile(Config::BIOS7Path, "rb");
if (!f)
{
printf("ARM7 BIOS not found\n");
for (i = 0; i < 16; i++)
((u32*)ARM7BIOS)[i] = 0xE7FFDEFF;
}
else
{
fseek(f, 0, SEEK_SET);
fread(ARM7BIOS, 0x4000, 1, f);
printf("ARM7 BIOS loaded\n");
fclose(f);
}
#ifdef JIT_ENABLED
ARMJIT::Reset();
#endif
if (ConsoleType == 1)
{
DSi::LoadBIOS();
DSi::LoadNAND();
ARM9ClockShift = 2;
MainRAMMask = 0xFFFFFF;
}
else
{
ARM9ClockShift = 1;
MainRAMMask = 0x3FFFFF;
}
// has to be called before InitTimings
// otherwise some PU settings are completely
// unitialised on the first run
ARM9->CP15Reset();
ARM9Timestamp = 0; ARM9Target = 0;
ARM7Timestamp = 0; ARM7Target = 0;
SysTimestamp = 0;
InitTimings();
memset(MainRAM, 0, MainRAMMask + 1);
memset(SharedWRAM, 0, 0x8000);
memset(ARM7WRAM, 0, 0x10000);
MapSharedWRAM(0);
ExMemCnt[0] = 0x4000;
ExMemCnt[1] = 0x4000;
memset(ROMSeed0, 0, 2*8);
memset(ROMSeed1, 0, 2*8);
SetGBASlotTimings();
IME[0] = 0;
IE[0] = 0;
IF[0] = 0;
IME[1] = 0;
IE[1] = 0;
IF[1] = 0;
IE2 = 0;
IF2 = 0;
PostFlag9 = 0x00;
PostFlag7 = 0x00;
PowerControl9 = 0x0001;
PowerControl7 = 0x0001;
WifiWaitCnt = 0xFFFF; // temp
SetWifiWaitCnt(0);
ARM7BIOSProt = 0;
IPCSync9 = 0;
IPCSync7 = 0;
IPCFIFOCnt9 = 0;
IPCFIFOCnt7 = 0;
IPCFIFO9.Clear();
IPCFIFO7.Clear();
DivCnt = 0;
SqrtCnt = 0;
ARM9->Reset();
ARM7->Reset();
CPUStop = 0;
memset(Timers, 0, 8*sizeof(Timer));
TimerCheckMask[0] = 0;
TimerCheckMask[1] = 0;
TimerTimestamp[0] = 0;
TimerTimestamp[1] = 0;
for (i = 0; i < 8; i++) DMAs[i]->Reset();
memset(DMA9Fill, 0, 4*4);
memset(SchedList, 0, sizeof(SchedList));
SchedListMask = 0;
KeyInput = 0x007F03FF;
KeyCnt = 0;
RCnt = 0;
NDSCart::Reset();
GBACart::Reset();
GPU::Reset();
SPU::Reset();
SPI::Reset();
RTC::Reset();
Wifi::Reset();
if (ConsoleType == 1)
{
DSi::Reset();
KeyInput &= ~(1 << (16+6));
}
AREngine::Reset();
}
void Stop()
{
printf("Stopping: shutdown\n");
Running = false;
Platform::StopEmu();
GPU::Stop();
SPU::Stop();
}
bool DoSavestate_Scheduler(Savestate* file)
{
// this is a bit of a hack
// but uh, your local coder realized that the scheduler list contains function pointers
// and that storing those as-is is not a very good idea
// unless you want it to crash and burn
// this is the solution your local coder came up with.
// it's gross but I think it's the best solution for this problem.
// just remember to add here if you add more event callbacks, kay?
// atleast until we come up with something more elegant.
void (*eventfuncs[])(u32) =
{
GPU::StartScanline, GPU::StartHBlank, GPU::FinishFrame,
SPU::Mix,
Wifi::USTimer,
GPU::DisplayFIFO,
NDSCart::ROMPrepareData, NDSCart::ROMEndTransfer,
NDSCart::SPITransferDone,
SPI::TransferDone,
DivDone,
SqrtDone,
NULL
};
int len = Event_MAX;
if (file->Saving)
{
for (int i = 0; i < len; i++)
{
SchedEvent* evt = &SchedList[i];
u32 funcid = -1;
if (evt->Func)
{
for (int j = 0; eventfuncs[j]; j++)
{
if (evt->Func == eventfuncs[j])
{
funcid = j;
break;
}
}
if (funcid == -1)
{
printf("savestate: VERY BAD!!!!! FUNCTION POINTER FOR EVENT %d NOT IN HACKY LIST. CANNOT SAVE. SMACK ARISOTURA.\n", i);
return false;
}
}
file->Var32(&funcid);
file->Var64(&evt->Timestamp);
file->Var32(&evt->Param);
}
}
else
{
for (int i = 0; i < len; i++)
{
SchedEvent* evt = &SchedList[i];
u32 funcid;
file->Var32(&funcid);
if (funcid != -1)
{
for (int j = 0; ; j++)
{
if (!eventfuncs[j])
{
printf("savestate: VERY BAD!!!!!! EVENT FUNCTION POINTER ID %d IS OUT OF RANGE. HAX?????\n", j);
return false;
}
if (j == funcid) break;
}
evt->Func = eventfuncs[funcid];
}
else
evt->Func = NULL;
file->Var64(&evt->Timestamp);
file->Var32(&evt->Param);
}
}
return true;
}
bool DoSavestate(Savestate* file)
{
file->Section("NDSG");
// TODO:
// * do something for bool's (sizeof=1)
// * do something for 'loading DSi-mode savestate in DS mode' and vice-versa
// * add IE2/IF2 there
file->VarArray(MainRAM, 0x400000);
file->VarArray(SharedWRAM, 0x8000);
file->VarArray(ARM7WRAM, ARM7WRAMSize);
file->VarArray(ExMemCnt, 2*sizeof(u16));
file->VarArray(ROMSeed0, 2*8);
file->VarArray(ROMSeed1, 2*8);
file->Var16(&WifiWaitCnt);
file->VarArray(IME, 2*sizeof(u32));
file->VarArray(IE, 2*sizeof(u32));
file->VarArray(IF, 2*sizeof(u32));
file->Var8(&PostFlag9);
file->Var8(&PostFlag7);
file->Var16(&PowerControl9);
file->Var16(&PowerControl7);
file->Var16(&ARM7BIOSProt);
file->Var16(&IPCSync9);
file->Var16(&IPCSync7);
file->Var16(&IPCFIFOCnt9);
file->Var16(&IPCFIFOCnt7);
IPCFIFO9.DoSavestate(file);
IPCFIFO7.DoSavestate(file);
file->Var16(&DivCnt);
file->Var16(&SqrtCnt);
file->Var32(&CPUStop);
for (int i = 0; i < 8; i++)
{
Timer* timer = &Timers[i];
file->Var16(&timer->Reload);
file->Var16(&timer->Cnt);
file->Var32(&timer->Counter);
file->Var32(&timer->CycleShift);
}
file->VarArray(TimerCheckMask, 2*sizeof(u8));
file->VarArray(TimerTimestamp, 2*sizeof(u64));
file->VarArray(DMA9Fill, 4*sizeof(u32));
if (!DoSavestate_Scheduler(file)) return false;
file->Var32(&SchedListMask);
file->Var64(&ARM9Timestamp);
file->Var64(&ARM9Target);
file->Var64(&ARM7Timestamp);
file->Var64(&ARM7Target);
file->Var64(&SysTimestamp);
file->Var64(&LastSysClockCycles);
file->Var64(&FrameStartTimestamp);
file->Var32(&NumFrames);
if (file->IsAtleastVersion(7, 1))
{
file->Var32(&NumLagFrames);
file->Bool32(&LagFrameFlag);
}
// TODO: save KeyInput????
file->Var16(&KeyCnt);
file->Var16(&RCnt);
file->Var8(&WRAMCnt);
file->Bool32(&RunningGame);
if (!file->Saving)
{
// 'dept of redundancy dept'
// but we do need to update the mappings
MapSharedWRAM(WRAMCnt);
InitTimings();
SetGBASlotTimings();
u16 tmp = WifiWaitCnt;
WifiWaitCnt = 0xFFFF;
SetWifiWaitCnt(tmp); // force timing table update
}
for (int i = 0; i < 8; i++)
DMAs[i]->DoSavestate(file);
ARM9->DoSavestate(file);
ARM7->DoSavestate(file);
NDSCart::DoSavestate(file);
GBACart::DoSavestate(file);
GPU::DoSavestate(file);
SPU::DoSavestate(file);
SPI::DoSavestate(file);
RTC::DoSavestate(file);
Wifi::DoSavestate(file);
if (!file->Saving)
{
GPU::SetPowerCnt(PowerControl9);
}
#ifdef JIT_ENABLED
if (!file->Saving)
{
ARMJIT::ResetBlockCache();
ARMJIT_Memory::Reset();
}
#endif
return true;
}
void SetConsoleType(int type)
{
ConsoleType = type;
}
bool LoadROM(const u8* romdata, u32 filelength, const char *sram, bool direct)
{
if (NDSCart::LoadROM(romdata, filelength, sram, direct))
{
Running = true;
return true;
}
else
{
printf("Failed to load ROM from archive\n");
return false;
}
}
bool LoadROM(const char* path, const char* sram, bool direct)
{
if (NDSCart::LoadROM(path, sram, direct))
{
Running = true;
return true;
}
else
{
printf("Failed to load ROM %s\n", path);
return false;
}
}
bool LoadGBAROM(const char* path, const char* sram)
{
if (GBACart::LoadROM(path, sram))
{
return true;
}
else
{
printf("Failed to load ROM %s\n", path);
return false;
}
}
bool LoadGBAROM(const u8* romdata, u32 filelength, const char *filename, const char *sram)
{
if (GBACart::LoadROM(romdata, filelength, sram))
{
return true;
}
else
{
printf("Failed to load ROM %s from archive\n", filename);
return false;
}
}
void LoadBIOS()
{
Reset();
Running = true;
}
void RelocateSave(const char* path, bool write)
{
printf("SRAM: relocating to %s (write=%s)\n", path, write?"true":"false");
NDSCart::RelocateSave(path, write);
}
u64 NextTarget()
{
u64 ret = SysTimestamp + kMaxIterationCycles;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (mask & 0x1)
{
if (SchedList[i].Timestamp < ret)
ret = SchedList[i].Timestamp;
}
mask >>= 1;
}
return ret;
}
void RunSystem(u64 timestamp)
{
SysTimestamp = timestamp;
u32 mask = SchedListMask;
for (int i = 0; i < Event_MAX; i++)
{
if (!mask) break;
if (mask & 0x1)
{
if (SchedList[i].Timestamp <= SysTimestamp)
{
SchedListMask &= ~(1<<i);
SchedList[i].Func(SchedList[i].Param);
}
}
mask >>= 1;
}
}
template <bool EnableJIT, int ConsoleType>
u32 RunFrame()
{
FrameStartTimestamp = SysTimestamp;
LagFrameFlag = true;
bool runFrame = Running && !(CPUStop & 0x40000000);
if (runFrame)
{
GPU::StartFrame();
while (Running && GPU::TotalScanlines==0)
{
// TODO: give it some margin, so it can directly do 17 cycles instead of 16 then 1
u64 target = NextTarget();
ARM9Target = target << ARM9ClockShift;
CurCPU = 0;
if (CPUStop & 0x80000000)
{
// GXFIFO stall
s32 cycles = GPU3D::CyclesToRunFor();
ARM9Timestamp = std::min(ARM9Target, ARM9Timestamp+(cycles<<ARM9ClockShift));
}
else if (CPUStop & 0x0FFF)
{
DMAs[0]->Run<ConsoleType>();
if (!(CPUStop & 0x80000000)) DMAs[1]->Run<ConsoleType>();
if (!(CPUStop & 0x80000000)) DMAs[2]->Run<ConsoleType>();
if (!(CPUStop & 0x80000000)) DMAs[3]->Run<ConsoleType>();
if (ConsoleType == 1) DSi::RunNDMAs(0);
}
else
{
#ifdef JIT_ENABLED
if (EnableJIT)
ARM9->ExecuteJIT();
else
#endif
ARM9->Execute();
}
RunTimers(0);
GPU3D::Run();
target = ARM9Timestamp >> ARM9ClockShift;
CurCPU = 1;
while (ARM7Timestamp < target)
{
ARM7Target = target; // might be changed by a reschedule
if (CPUStop & 0x0FFF0000)
{
DMAs[4]->Run<ConsoleType>();
DMAs[5]->Run<ConsoleType>();
DMAs[6]->Run<ConsoleType>();
DMAs[7]->Run<ConsoleType>();