aiqinger

aiqinger

Stars

4 stars written in Verilog

[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)

Verilog 41 9 Updated Mar 30, 2021

Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 2022

Verilog 16 Updated Dec 9, 2022

Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".

Verilog 10 Updated Jun 25, 2020

Approximation-Aware Functional Reverse Engineering using Graph Neural Networks

Verilog 9 1 Updated Oct 30, 2022