opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

An Open-source FPGA IP Generator

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

Re-coded Xilinx primitives for Verilator use