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Commits on Jun 18, 2024

• Add the quick start document.

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Commits on Jun 17, 2024

• target/riscv: Use BIT_ULL() to ensure 64-bit operation in Windows.

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Commits on May 23, 2024

• target/riscv: Add more options to andes.cfg. (qemu#145)

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Commits on May 22, 2024

• hw/riscv: Remove lm properties of riscv_hart. (qemu#146)

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Commits on May 21, 2024

• target/riscv: Fixed the hart_id assumption that is made in the PLMT. (qemu#143)

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• hw/riscv: Add support of Andes HVM. (qemu#144)

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Commits on May 7, 2024

• target/riscv: Handle exceptions and non-external interrupts in VEC_PLIC mode. (qemu#142)

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Commits on May 6, 2024

• target/riscv: Raise an exception when CoDense insn finds a 16-bit insn.

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• target/riscv: Add Andes DSP extension(p extension 0.5.2) support. (qemu#141)

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Commits on Apr 30, 2024

• target/riscv: Adjust behavior of debug spec for Andes cores.

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• target/riscv: Adjust write mask of mstatus for Andes cores.

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• target/riscv: Add write mask of mcounteren for Andes cores.

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• target/riscv: Add support of "mmsc-cfg-rvarch2" property to andes.cfg.

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Commits on Apr 29, 2024

• target/riscv: Fix the check of vectored PLIC external interrupts. (qemu#140)

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• target/riscv: Add behaviors of mcounterovf for N25 and other CPUs.

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Commits on Apr 18, 2024

• target/riscv: Fix GDB can not read the read-only CSR

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• target/riscv: Fix HSP cosim issues. (qemu#138)

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Commits on Apr 16, 2024

• atcsmu: Implement SYSTEMVER, BOARDVER, SYSTEMCFG, and SMUVER

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Commits on Apr 15, 2024

• target/riscv: Add support of "ecc" property to andes.cfg.

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• target/riscv: Add initial marchid.Commercial bit to Andes cores.

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• target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

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Commits on Apr 8, 2024

• target/riscv: Fix index of fired breakpoint and watchpoint

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• atcdmac300: Implement ID and revision register

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Commits on Apr 3, 2024

• target/riscv: Enable MMSC_CFG_PPMA bit of andes_ax25 for linux check.

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Commits on Apr 2, 2024

• target/riscv: Enable MMSC_CFG_PPMA bit of andes_a25 for linux check.

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Commits on Mar 20, 2024

• target/riscv: Fix HSP bugs.

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Commits on Mar 15, 2024

• target/riscv: Add cpu property 'XAndesBiuAddrWidth'.

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Commits on Mar 8, 2024

• atcrtc100: interrupt update after writing interrupt status (qemu#127)

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  Ethan Chen

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• target/riscv: Sync mmsc_cfg values of A25/AX25/A27L2/AX27L2 with ast530 release FPGA bitmap (qemu#130)

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  Leo Yu-Chi Liang

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Commits on Mar 5, 2024

• hw/intc: fix andes_plic_write comment typo

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  Leo Yu-Chi Liang

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• hw/intc: Support "Number of Interrupt and Target Configuration Register" for PLIC[SW]

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  Leo Yu-Chi Liang

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Commits on Feb 29, 2024

• hw: dma: atcdmac300: De-assert the DMA IRQ signal when no interrupt

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• hw/intc: Support trigger type of PLIC (qemu#124)

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Commits on Feb 22, 2024

• target/riscv: Support compile QEMU on MSYS2 with MingW W32 platform

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Commits on Feb 21, 2024

• target/riscv: Check mslideleg to decide the read/write behaviors of slie/slip. (qemu#122)

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