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Commits on Apr 18, 2024

• target/riscv: Fix HSP cosim issues. (qemu#138)

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Commits on Apr 16, 2024

• atcsmu: Implement SYSTEMVER, BOARDVER, SYSTEMCFG, and SMUVER

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Commits on Apr 15, 2024

• target/riscv: Add support of "ecc" property to andes.cfg.

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• target/riscv: Add initial marchid.Commercial bit to Andes cores.

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• target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

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Commits on Apr 8, 2024

• target/riscv: Fix index of fired breakpoint and watchpoint

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• atcdmac300: Implement ID and revision register

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Commits on Apr 3, 2024

• target/riscv: Enable MMSC_CFG_PPMA bit of andes_ax25 for linux check.

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Commits on Apr 2, 2024

• target/riscv: Enable MMSC_CFG_PPMA bit of andes_a25 for linux check.

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Commits on Mar 20, 2024

• target/riscv: Fix HSP bugs.

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Commits on Mar 15, 2024

• target/riscv: Add cpu property 'XAndesBiuAddrWidth'.

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Commits on Mar 8, 2024

• atcrtc100: interrupt update after writing interrupt status (qemu#127)

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  Ethan Chen

  authored and

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• target/riscv: Sync mmsc_cfg values of A25/AX25/A27L2/AX27L2 with ast530 release FPGA bitmap (qemu#130)

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  Leo Yu-Chi Liang

  and

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Commits on Mar 5, 2024

• hw/intc: fix andes_plic_write comment typo

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  Leo Yu-Chi Liang

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• hw/intc: Support "Number of Interrupt and Target Configuration Register" for PLIC[SW]

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  Leo Yu-Chi Liang

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Commits on Feb 29, 2024

• hw: dma: atcdmac300: De-assert the DMA IRQ signal when no interrupt

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• hw/intc: Support trigger type of PLIC (qemu#124)

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Commits on Feb 22, 2024

• target/riscv: Support compile QEMU on MSYS2 with MingW W32 platform

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Commits on Feb 21, 2024

• target/riscv: Check mslideleg to decide the read/write behaviors of slie/slip. (qemu#122)

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• gdbstub: Fix and enhance 'nds read_acedesc' command feature

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Commits on Feb 15, 2024

• target/riscv: Remove specific csr code.

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• target/riscv: Remove the usage of g_alloca0() for Ubuntu 20.04.

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Commits on Feb 7, 2024

• target/riscv: Initializie UXL/SXL of mstatus only when the U/S mode is implemented.

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Commits on Feb 1, 2024

• target/riscv: Use glib2 APIs to instead of standard C

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• gdbstub: Refine ACE debugger relative code

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• gdbstub: Add support of monitor command "nds va on/off". (qemu#118) (qemu#119)

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Commits on Jan 30, 2024

• target/riscv: Modularize register writing of type 15 trigger

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Commits on Jan 29, 2024

• target/riscv: Add checking riscv_timebase_freq value which is coming from readconfig

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• docs/config: Add more comments for andes configuration

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• hw/riscv: local memory: Fix local memory size and base (qemu#116)

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  Ethan Chen

  committed
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• target/riscv: Enlarge the number of trigger to 8

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• target/riscv: Directly write tdata1 type = 15 also disables the trigger

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• target/riscv: Fix log typo for TRIGGER_TYPE_NO_EXIST

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• target/riscv: Set the version of Sdtrig extension info CSR tinfo

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• target/riscv: Do not ignore dmode field when trigger type is disabled

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