PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog AXI components for FPGA implementation

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

Re-coded Xilinx primitives for Verilator use