Skip to content

Commit 0aea96d

Browse files
gmarullcarlescufi
gmarull
authored and
carlescufi
committed
drivers: pwm: minor formatting enhancements
Some formatting tweaks to improve the outcome of clang-format. Signed-off-by: Gerard Marull-Paretas <[email protected]>
1 parent c82d71e commit 0aea96d

18 files changed

+31
-17
lines changed

‎drivers/pwm/pwm_gd32.c

+1
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <gd32_timer.h>
1717

1818
#include <zephyr/logging/log.h>
19+
1920
LOG_MODULE_REGISTER(pwm_gd32, CONFIG_PWM_LOG_LEVEL);
2021

2122
/** PWM data. */

‎drivers/pwm/pwm_gecko.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ static int pwm_gecko_get_cycles_per_sec(const struct device *dev,
7474

7575
static const struct pwm_driver_api pwm_gecko_driver_api = {
7676
.set_cycles = pwm_gecko_set_cycles,
77-
.get_cycles_per_sec = pwm_gecko_get_cycles_per_sec
77+
.get_cycles_per_sec = pwm_gecko_get_cycles_per_sec,
7878
};
7979

8080
static int pwm_gecko_init(const struct device *dev)

‎drivers/pwm/pwm_imx.c

+1
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <zephyr/drivers/pinctrl.h>
1212

1313
#include <zephyr/logging/log.h>
14+
1415
LOG_MODULE_REGISTER(pwm_imx, CONFIG_PWM_LOG_LEVEL);
1516

1617
#define PWM_PWMSR_FIFOAV_4WORDS 0x4

‎drivers/pwm/pwm_ite_it8xxx2.c

+1
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include <stdlib.h>
1818

1919
#include <zephyr/logging/log.h>
20+
2021
LOG_MODULE_REGISTER(pwm_ite_it8xxx2, CONFIG_PWM_LOG_LEVEL);
2122

2223
#define PWM_CTRX_MIN 100

‎drivers/pwm/pwm_mchp_xec.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ static const uint32_t max_freq_high_on_div[NUM_DIV_ELEMS] = {
8484
3692307,
8585
3428571,
8686
3200000,
87-
3000000
87+
3000000,
8888
};
8989

9090
static const uint32_t max_freq_low_on_div[NUM_DIV_ELEMS] = {
@@ -103,7 +103,7 @@ static const uint32_t max_freq_low_on_div[NUM_DIV_ELEMS] = {
103103
7692,
104104
7142,
105105
6666,
106-
6250
106+
6250,
107107
};
108108

109109
static uint32_t xec_compute_frequency(uint32_t clk, uint32_t on, uint32_t off)

‎drivers/pwm/pwm_mcux.c

+1
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include <zephyr/drivers/pinctrl.h>
1515

1616
#include <zephyr/logging/log.h>
17+
1718
LOG_MODULE_REGISTER(pwm_mcux, CONFIG_PWM_LOG_LEVEL);
1819

1920
#define CHANNEL_COUNT 2

‎drivers/pwm/pwm_mcux_ftm.c

+1
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <zephyr/drivers/pinctrl.h>
1717

1818
#include <zephyr/logging/log.h>
19+
1920
LOG_MODULE_REGISTER(pwm_mcux_ftm, CONFIG_PWM_LOG_LEVEL);
2021

2122
#define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)

‎drivers/pwm/pwm_mcux_pwt.c

+1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <zephyr/drivers/pinctrl.h>
1616

1717
#include <zephyr/logging/log.h>
18+
1819
LOG_MODULE_REGISTER(pwm_mcux_pwt, CONFIG_PWM_LOG_LEVEL);
1920

2021
/* Number of PWT input ports */

‎drivers/pwm/pwm_mcux_sctimer.c

+1
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#endif
1717

1818
#include <zephyr/logging/log.h>
19+
1920
LOG_MODULE_REGISTER(pwm_mcux_sctimer, CONFIG_PWM_LOG_LEVEL);
2021

2122
#define CHANNEL_COUNT FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS

‎drivers/pwm/pwm_mcux_tpm.c

+1
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include <zephyr/drivers/pinctrl.h>
2020

2121
#include <zephyr/logging/log.h>
22+
2223
LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
2324

2425
#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)

‎drivers/pwm/pwm_npcx.c

+1
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include <soc.h>
1515

1616
#include <zephyr/logging/log.h>
17+
1718
LOG_MODULE_REGISTER(pwm_npcx, LOG_LEVEL_ERR);
1819

1920
/* 16-bit period cycles/prescaler in NPCX PWM modules */

‎drivers/pwm/pwm_nrf5_sw.c

+12-11
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <nrf_peripherals.h>
1616

1717
#include <zephyr/logging/log.h>
18+
1819
LOG_MODULE_REGISTER(pwm_nrf5_sw, CONFIG_PWM_LOG_LEVEL);
1920

2021
#define GENERATOR_NODE DT_INST_PHANDLE(0, generator)
@@ -232,31 +233,31 @@ static int pwm_nrf5_sw_set_cycles(const struct device *dev, uint32_t channel,
232233
/* setup PPI */
233234
if (USE_RTC) {
234235
NRF_PPI->CH[ppi_chs[0]].EEP =
235-
(uint32_t) &(rtc->EVENTS_COMPARE[1 + channel]);
236+
(uint32_t) &rtc->EVENTS_COMPARE[1 + channel];
236237
NRF_PPI->CH[ppi_chs[0]].TEP =
237-
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
238+
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
238239
NRF_PPI->CH[ppi_chs[1]].EEP =
239-
(uint32_t) &(rtc->EVENTS_COMPARE[0]);
240+
(uint32_t) &rtc->EVENTS_COMPARE[0];
240241
NRF_PPI->CH[ppi_chs[1]].TEP =
241-
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
242+
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
242243
#if defined(PPI_FEATURE_FORKS_PRESENT)
243244
NRF_PPI->FORK[ppi_chs[1]].TEP =
244-
(uint32_t) &(rtc->TASKS_CLEAR);
245+
(uint32_t) &rtc->TASKS_CLEAR;
245246
#else
246247
NRF_PPI->CH[ppi_chs[2]].EEP =
247-
(uint32_t) &(rtc->EVENTS_COMPARE[0]);
248+
(uint32_t) &rtc->EVENTS_COMPARE[0];
248249
NRF_PPI->CH[ppi_chs[2]].TEP =
249-
(uint32_t) &(rtc->TASKS_CLEAR);
250+
(uint32_t) &rtc->TASKS_CLEAR;
250251
#endif
251252
} else {
252253
NRF_PPI->CH[ppi_chs[0]].EEP =
253-
(uint32_t) &(timer->EVENTS_COMPARE[1 + channel]);
254+
(uint32_t) &timer->EVENTS_COMPARE[1 + channel];
254255
NRF_PPI->CH[ppi_chs[0]].TEP =
255-
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
256+
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
256257
NRF_PPI->CH[ppi_chs[1]].EEP =
257-
(uint32_t) &(timer->EVENTS_COMPARE[0]);
258+
(uint32_t) &timer->EVENTS_COMPARE[0];
258259
NRF_PPI->CH[ppi_chs[1]].TEP =
259-
(uint32_t) &(NRF_GPIOTE->TASKS_OUT[gpiote_ch]);
260+
(uint32_t) &NRF_GPIOTE->TASKS_OUT[gpiote_ch];
260261
}
261262
NRF_PPI->CHENSET = ppi_mask;
262263

‎drivers/pwm/pwm_nrfx.c

+1
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include <stdbool.h>
1313

1414
#include <zephyr/logging/log.h>
15+
1516
LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
1617

1718
#define PWM_NRFX_CH_POLARITY_MASK BIT(15)

‎drivers/pwm/pwm_rv32m1_tpm.c

+1
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#endif
2121

2222
#include <zephyr/logging/log.h>
23+
2324
LOG_MODULE_REGISTER(pwm_rv32m1_tpm, CONFIG_PWM_LOG_LEVEL);
2425

2526
#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)

‎drivers/pwm/pwm_sam.c

+1
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <soc.h>
1414

1515
#include <zephyr/logging/log.h>
16+
1617
LOG_MODULE_REGISTER(pwm_sam, CONFIG_PWM_LOG_LEVEL);
1718

1819
struct sam_pwm_config {

‎drivers/pwm/pwm_sifive.c

+2-3
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,14 @@
77
#define DT_DRV_COMPAT sifive_pwm0
88

99
#include <zephyr/logging/log.h>
10-
11-
LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
12-
1310
#include <zephyr/sys/sys_io.h>
1411
#include <zephyr/device.h>
1512
#include <zephyr/drivers/pinctrl.h>
1613
#include <zephyr/drivers/pwm.h>
1714
#include <soc.h>
1815

16+
LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
17+
1918
/* Macros */
2019

2120
#define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))

‎drivers/pwm/pwm_stm32.c

+1
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
2323

2424
#include <zephyr/logging/log.h>
25+
2526
LOG_MODULE_REGISTER(pwm_stm32, CONFIG_PWM_LOG_LEVEL);
2627

2728
/* L0 series MCUs only have 16-bit timers and don't have below macro defined */

‎drivers/pwm/pwm_xlnx_axi_timer.c

+1
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include <zephyr/drivers/pwm.h>
1111
#include <zephyr/sys/sys_io.h>
1212
#include <zephyr/logging/log.h>
13+
1314
LOG_MODULE_REGISTER(xlnx_axi_timer_pwm, CONFIG_PWM_LOG_LEVEL);
1415

1516
/* AXI Timer v2.0 registers offsets (See Xilinx PG079 for details) */

0 commit comments

Comments
 (0)