drivers: gic: Redistributor Power Register

GIC-600 and later interrupt controllers have an additional
GICR_PWRR register that controls the power up sequencing
of the redistributors.  Added logic to gicv3_rdist_enable to
configure GICR_PWRR if required.

Signed-off-by: Chad Karaginides <[email protected]>

Author: quic-chadk

drivers/interrupt_controller/intc_gicv3.c

@@ -299,6 +299,16 @@ static void gicv3_rdist_enable(mem_addr_t rdist)
 		return;
 	}
 
+	if (GICR_IIDR_PRODUCT_ID_GET(sys_read32(rdist + GICR_IIDR)) >= 0x2) {
+		if (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) {
+			sys_set_bit(rdist + GICR_PWRR, GICR_PWRR_RDAG);
+			sys_clear_bit(rdist + GICR_PWRR, GICR_PWRR_RDPD);
+			while (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) {
+				;
+			}
+		}
+	}
+
 	sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
 	while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)) {
 		;

drivers/interrupt_controller/intc_gicv3_priv.h

@@ -41,6 +41,7 @@
 #define GICR_TYPER			0x0008
 #define GICR_STATUSR			0x0010
 #define GICR_WAKER			0x0014
+#define GICR_PWRR			0x0024
 #define GICR_PROPBASER			0x0070
 #define GICR_PENDBASER			0x0078
 
@@ -62,6 +63,11 @@
 #define GICR_CTLR_ENABLE_LPIS		BIT(0)
 #define GICR_CTLR_RWP			3
 
+/* GICR_IIDR */
+#define GICR_IIDR_PRODUCT_ID_SHIFT		24
+#define GICR_IIDR_PRODUCT_ID_MASK		0xFFUL
+#define GICR_IIDR_PRODUCT_ID_GET(_val)		MASK_GET(_val, GICR_IIDR_PRODUCT_ID)
+
 /* GICR_TYPER */
 #define GICR_TYPER_AFFINITY_VALUE_SHIFT		32
 #define GICR_TYPER_AFFINITY_VALUE_MASK		0xFFFFFFFFUL
@@ -77,6 +83,11 @@
 #define GICR_WAKER_PS			1
 #define GICR_WAKER_CA			2
 
+/* GICR_PWRR */
+#define GICR_PWRR_RDPD			0
+#define GICR_PWRR_RDAG			1
+#define GICR_PWRR_RDGPO			3
+
 /* GICR_PROPBASER */
 #define GITR_PROPBASER_ID_BITS_MASK		0x1fUL
 #define GITR_PROPBASER_INNER_CACHE_SHIFT	7