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Roberto Medinacarlescufi
Roberto Medina
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carlescufi
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arch: arm64: add support for coredump
* Add support for coredump on ARM64 architectures. * Add the script used for post-processing coredump output. Signed-off-by: Marcelo Ruaro <[email protected]> Signed-off-by: Rodrigo Cataldo <[email protected]> Signed-off-by: Roberto Medina <[email protected]>
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‎arch/Kconfig

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@@ -43,6 +43,7 @@ config ARM64
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select ARCH_IS_SET
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select 64BIT
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select HAS_DTS
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select ARCH_SUPPORTS_COREDUMP
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select HAS_ARM_SMCCC
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select ARCH_HAS_THREAD_LOCAL_STORAGE
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select USE_SWITCH

‎arch/arm64/core/CMakeLists.txt

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@@ -37,6 +37,7 @@ zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
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zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S)
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zephyr_library_sources_ifdef(CONFIG_AARCH64_IMAGE_HEADER header.S)
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zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
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zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
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if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
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zephyr_library_sources(smp.c)
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endif ()

‎arch/arm64/core/coredump.c

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@@ -0,0 +1,105 @@
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/*
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* Copyright (c) 2022 Huawei Technologies SASU
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <zephyr/debug/coredump.h>
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/* Identify the version of this block (in case of architecture changes).
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* To be interpreted by the target architecture specific block parser.
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*/
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#define ARCH_HDR_VER 1
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/* Structure to store the architecture registers passed arch_coredump_info_dump
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* As callee saved registers are not provided in z_arch_esf_t structure in Zephyr
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* we just need 22 registers.
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*/
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struct arm64_arch_block {
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struct {
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uint64_t x0;
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uint64_t x1;
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uint64_t x2;
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uint64_t x3;
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uint64_t x4;
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uint64_t x5;
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uint64_t x6;
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uint64_t x7;
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uint64_t x8;
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uint64_t x9;
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uint64_t x10;
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uint64_t x11;
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uint64_t x12;
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uint64_t x13;
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uint64_t x14;
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uint64_t x15;
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uint64_t x16;
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uint64_t x17;
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uint64_t x18;
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uint64_t lr;
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uint64_t spsr;
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uint64_t elr;
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} r;
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} __packed;
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/*
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* Register block takes up too much stack space
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* if defined within function. So define it here.
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*/
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static struct arm64_arch_block arch_blk;
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void arch_coredump_info_dump(const z_arch_esf_t *esf)
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{
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/* Target architecture information header */
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/* Information just relevant to the python parser */
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struct coredump_arch_hdr_t hdr = {
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.id = COREDUMP_ARCH_HDR_ID,
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.hdr_version = ARCH_HDR_VER,
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.num_bytes = sizeof(arch_blk),
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};
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/* Nothing to process */
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if (esf == NULL) {
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return;
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}
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(void)memset(&arch_blk, 0, sizeof(arch_blk));
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/*
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* Copies the thread registers to a memory block that will be printed out
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* The thread registers are already provided by structure z_arch_esf_t
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*/
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arch_blk.r.x0 = esf->x0;
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arch_blk.r.x1 = esf->x1;
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arch_blk.r.x2 = esf->x2;
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arch_blk.r.x3 = esf->x3;
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arch_blk.r.x4 = esf->x4;
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arch_blk.r.x5 = esf->x5;
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arch_blk.r.x6 = esf->x6;
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arch_blk.r.x7 = esf->x7;
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arch_blk.r.x8 = esf->x8;
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arch_blk.r.x9 = esf->x9;
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arch_blk.r.x10 = esf->x10;
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arch_blk.r.x11 = esf->x11;
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arch_blk.r.x12 = esf->x12;
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arch_blk.r.x13 = esf->x13;
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arch_blk.r.x14 = esf->x14;
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arch_blk.r.x15 = esf->x15;
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arch_blk.r.x16 = esf->x16;
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arch_blk.r.x17 = esf->x17;
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arch_blk.r.x18 = esf->x18;
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arch_blk.r.lr = esf->lr;
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arch_blk.r.spsr = esf->spsr;
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arch_blk.r.elr = esf->elr;
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/* Send for output */
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coredump_buffer_output((uint8_t *)&hdr, sizeof(hdr));
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coredump_buffer_output((uint8_t *)&arch_blk, sizeof(arch_blk));
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}
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uint16_t arch_coredump_tgt_code_get(void)
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{
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return COREDUMP_TGT_ARM64;
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}

‎include/zephyr/debug/coredump.h

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@@ -123,6 +123,7 @@ enum coredump_tgt_code {
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COREDUMP_TGT_ARM_CORTEX_M,
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COREDUMP_TGT_RISC_V,
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COREDUMP_TGT_XTENSA,
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COREDUMP_TGT_ARM64,
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};
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/* Coredump header */

‎scripts/coredump/gdbstubs/__init__.py

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@@ -9,6 +9,7 @@
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from gdbstubs.arch.arm_cortex_m import GdbStub_ARM_CortexM
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from gdbstubs.arch.risc_v import GdbStub_RISC_V
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from gdbstubs.arch.xtensa import GdbStub_Xtensa
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from gdbstubs.arch.arm64 import GdbStub_ARM64
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class TgtCode:
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UNKNOWN = 0
@@ -17,6 +18,7 @@ class TgtCode:
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ARM_CORTEX_M = 3
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RISC_V = 4
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XTENSA = 5
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ARM64 = 6
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def get_gdbstub(logfile, elffile):
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stub = None
@@ -33,5 +35,7 @@ def get_gdbstub(logfile, elffile):
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stub = GdbStub_RISC_V(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.XTENSA:
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stub = GdbStub_Xtensa(logfile=logfile, elffile=elffile)
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elif tgt_code == TgtCode.ARM64:
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stub = GdbStub_ARM64(logfile=logfile, elffile=elffile)
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return stub

‎scripts/coredump/gdbstubs/arch/arm64.py

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@@ -0,0 +1,131 @@
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#!/usr/bin/env python3
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#
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# Copyright (c) 2022 Huawei Technologies SASU
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#
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# SPDX-License-Identifier: Apache-2.0
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import binascii
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import logging
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import struct
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from gdbstubs.gdbstub import GdbStub
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logger = logging.getLogger("gdbstub")
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class RegNum():
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X0 = 0 # X0-X29 - 30 GP registers
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X1 = 1
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X2 = 2
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X3 = 3
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X4 = 4
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X5 = 5
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X6 = 6
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X7 = 7
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X8 = 8
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X9 = 9
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X10 = 10
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X11 = 11
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X12 = 12
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X13 = 13
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X14 = 14
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X15 = 15
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X16 = 16
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X17 = 17
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X18 = 18
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X19 = 19
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X20 = 20
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X21 = 21
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X22 = 22
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X23 = 23
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X24 = 24
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X25 = 25
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X26 = 26
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X27 = 27
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X28 = 28
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X29 = 29 # Frame pointer register
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LR = 30 # X30 Link Register(LR)
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SP_EL0 = 31 # Stack pointer EL0 (SP_EL0)
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PC = 32 # Program Counter (PC)
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class GdbStub_ARM64(GdbStub):
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ARCH_DATA_BLK_STRUCT = "<QQQQQQQQQQQQQQQQQQQQQQ"
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# Default signal used by all other script, just using the same
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GDB_SIGNAL_DEFAULT = 7
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# The number of registers expected by GDB
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GDB_G_PKT_NUM_REGS = 33
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def __init__(self, logfile, elffile):
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super().__init__(logfile=logfile, elffile=elffile)
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self.registers = None
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self.gdb_signal = self.GDB_SIGNAL_DEFAULT
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self.parse_arch_data_block()
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def parse_arch_data_block(self):
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arch_data_blk = self.logfile.get_arch_data()['data']
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tu = struct.unpack(self.ARCH_DATA_BLK_STRUCT, arch_data_blk)
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self.registers = dict()
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self.registers[RegNum.X0] = tu[0]
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self.registers[RegNum.X1] = tu[1]
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self.registers[RegNum.X2] = tu[2]
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self.registers[RegNum.X3] = tu[3]
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self.registers[RegNum.X4] = tu[4]
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self.registers[RegNum.X5] = tu[5]
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self.registers[RegNum.X6] = tu[6]
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self.registers[RegNum.X7] = tu[7]
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self.registers[RegNum.X8] = tu[8]
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self.registers[RegNum.X9] = tu[9]
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self.registers[RegNum.X10] = tu[10]
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self.registers[RegNum.X11] = tu[11]
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self.registers[RegNum.X12] = tu[12]
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self.registers[RegNum.X13] = tu[13]
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self.registers[RegNum.X14] = tu[14]
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self.registers[RegNum.X15] = tu[15]
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self.registers[RegNum.X16] = tu[16]
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self.registers[RegNum.X17] = tu[17]
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self.registers[RegNum.X18] = tu[18]
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# Callee saved registers are not provided in __esf structure
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# So they will be omitted (set to undefined) when stub generates the
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# packet in handle_register_group_read_packet.
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self.registers[RegNum.LR] = tu[19]
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self.registers[RegNum.SP_EL0] = tu[20]
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self.registers[RegNum.PC] = tu[21]
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def handle_register_group_read_packet(self):
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reg_fmt = "<Q"
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idx = 0
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pkt = b''
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while idx < self.GDB_G_PKT_NUM_REGS:
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if idx in self.registers:
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bval = struct.pack(reg_fmt, self.registers[idx])
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pkt += binascii.hexlify(bval)
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else:
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# Register not in coredump -> unknown value
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# Send in "xxxxxxxx"
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pkt += b'x' * 16
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idx += 1
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self.put_gdb_packet(pkt)
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def handle_register_single_read_packet(self, pkt):
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# Mark registers as "<unavailable>".
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# 'p' packets are usually used for registers
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# other than the general ones (e.g. eax, ebx)
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# so we can safely reply "xxxxxxxx" here.
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self.put_gdb_packet(b'x' * 16)

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