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pdgendtcarlescufi
pdgendt
authored and
carlescufi
committed
treewide: Update clock control API usage
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t) Signed-off-by: Pieter De Gendt <[email protected]>
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88 files changed

+160
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lines changed

‎drivers/adc/adc_gd32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,7 @@ static int adc_gd32_init(const struct device *dev)
383383
#endif
384384

385385
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
386-
(clock_control_subsys_t *)&cfg->clkid);
386+
(clock_control_subsys_t)&cfg->clkid);
387387

388388
(void)reset_line_toggle_dt(&cfg->reset);
389389

‎drivers/adc/adc_npcx.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -784,14 +784,14 @@ static int adc_npcx_init(const struct device *dev)
784784
data->adc_dev = dev;
785785

786786
/* Turn on device clock first and get source clock freq. */
787-
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
787+
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
788788
&config->clk_cfg);
789789
if (ret < 0) {
790790
LOG_ERR("Turn on ADC clock fail %d", ret);
791791
return ret;
792792
}
793793

794-
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
794+
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t)
795795
&config->clk_cfg, &data->input_clk);
796796
if (ret < 0) {
797797
LOG_ERR("Get ADC clock rate error %d", ret);

‎drivers/adc/adc_sam_afec.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ static int adc_sam_init(const struct device *dev)
298298

299299
/* Enable AFEC clock in PMC */
300300
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
301-
(clock_control_subsys_t *)&cfg->clock_cfg);
301+
(clock_control_subsys_t)&cfg->clock_cfg);
302302

303303
/* Connect pins to the peripheral */
304304
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);

‎drivers/adc/adc_stm32.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -1366,7 +1366,7 @@ static int adc_stm32_init(const struct device *dev)
13661366
#endif
13671367

13681368
if (clock_control_on(clk,
1369-
(clock_control_subsys_t *) &config->pclken) != 0) {
1369+
(clock_control_subsys_t) &config->pclken) != 0) {
13701370
return -EIO;
13711371
}
13721372

@@ -1504,7 +1504,7 @@ static int adc_stm32_init(const struct device *dev)
15041504
uint32_t adc_rate, wait_cycles;
15051505

15061506
if (clock_control_get_rate(clk,
1507-
(clock_control_subsys_t *) &config->pclken, &adc_rate) < 0) {
1507+
(clock_control_subsys_t) &config->pclken, &adc_rate) < 0) {
15081508
LOG_ERR("ADC clock rate get error.");
15091509
}
15101510

‎drivers/can/can_rcar.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -1015,19 +1015,19 @@ static int can_rcar_init(const struct device *dev)
10151015

10161016
/* reset the registers */
10171017
ret = clock_control_off(config->clock_dev,
1018-
(clock_control_subsys_t *)&config->mod_clk);
1018+
(clock_control_subsys_t)&config->mod_clk);
10191019
if (ret < 0) {
10201020
return ret;
10211021
}
10221022

10231023
ret = clock_control_on(config->clock_dev,
1024-
(clock_control_subsys_t *)&config->mod_clk);
1024+
(clock_control_subsys_t)&config->mod_clk);
10251025
if (ret < 0) {
10261026
return ret;
10271027
}
10281028

10291029
ret = clock_control_on(config->clock_dev,
1030-
(clock_control_subsys_t *)&config->bus_clk);
1030+
(clock_control_subsys_t)&config->bus_clk);
10311031
if (ret < 0) {
10321032
return ret;
10331033
}

‎drivers/can/can_sam.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
4747

4848
/* Enable CAN clock in PMC */
4949
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
50-
(clock_control_subsys_t *)&sam_cfg->clock_cfg);
50+
(clock_control_subsys_t)&sam_cfg->clock_cfg);
5151
}
5252

5353
static int can_sam_init(const struct device *dev)

‎drivers/can/can_stm32.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -532,7 +532,7 @@ static int can_stm32_get_core_clock(const struct device *dev, uint32_t *rate)
532532
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
533533

534534
ret = clock_control_get_rate(clock,
535-
(clock_control_subsys_t *) &cfg->pclken,
535+
(clock_control_subsys_t) &cfg->pclken,
536536
rate);
537537
if (ret != 0) {
538538
LOG_ERR("Failed call clock_control_get_rate: return [%d]", ret);
@@ -589,7 +589,7 @@ static int can_stm32_init(const struct device *dev)
589589
return -ENODEV;
590590
}
591591

592-
ret = clock_control_on(clock, (clock_control_subsys_t *) &cfg->pclken);
592+
ret = clock_control_on(clock, (clock_control_subsys_t) &cfg->pclken);
593593
if (ret != 0) {
594594
LOG_ERR("HAL_CAN_Init clock control on failed: %d", ret);
595595
return -EIO;

‎drivers/can/can_stm32h7.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ static int can_stm32h7_clock_enable(const struct device *dev)
5858
return -ENODEV;
5959
}
6060

61-
ret = clock_control_on(clk, (clock_control_subsys_t *)&stm32h7_cfg->pclken);
61+
ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken);
6262
if (ret != 0) {
6363
LOG_ERR("failure enabling clock");
6464
return ret;

‎drivers/counter/counter_gd32_timer.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -431,9 +431,9 @@ static int counter_gd32_timer_init(const struct device *dev)
431431
uint32_t pclk;
432432

433433
clock_control_on(GD32_CLOCK_CONTROLLER,
434-
(clock_control_subsys_t *)&cfg->clkid);
434+
(clock_control_subsys_t)&cfg->clkid);
435435
clock_control_get_rate(GD32_CLOCK_CONTROLLER,
436-
(clock_control_subsys_t *)&cfg->clkid, &pclk);
436+
(clock_control_subsys_t)&cfg->clkid, &pclk);
437437

438438
data->freq = pclk / (cfg->prescaler + 1);
439439

‎drivers/counter/counter_ll_stm32_rtc.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -398,7 +398,7 @@ static int rtc_stm32_init(const struct device *dev)
398398
}
399399

400400
/* Enable RTC bus clock */
401-
if (clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken[0]) != 0) {
401+
if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
402402
LOG_ERR("clock op failed\n");
403403
return -EIO;
404404
}
@@ -411,7 +411,7 @@ static int rtc_stm32_init(const struct device *dev)
411411

412412
/* Enable RTC clock source */
413413
if (clock_control_configure(clk,
414-
(clock_control_subsys_t *) &cfg->pclken[1],
414+
(clock_control_subsys_t) &cfg->pclken[1],
415415
NULL) != 0) {
416416
LOG_ERR("clock configure failed\n");
417417
return -EIO;

‎drivers/counter/counter_ll_stm32_timer.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,7 @@ static int counter_stm32_get_tim_clk(const struct stm32_pclken *pclken, uint32_t
372372
return -ENODEV;
373373
}
374374

375-
r = clock_control_get_rate(clk, (clock_control_subsys_t *)pclken,
375+
r = clock_control_get_rate(clk, (clock_control_subsys_t)pclken,
376376
&bus_clk);
377377
if (r < 0) {
378378
return r;
@@ -458,7 +458,7 @@ static int counter_stm32_init_timer(const struct device *dev)
458458

459459
/* initialize clock and check its speed */
460460
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
461-
(clock_control_subsys_t *)&cfg->pclken);
461+
(clock_control_subsys_t)&cfg->pclken);
462462
if (r < 0) {
463463
LOG_ERR("Could not initialize clock (%d)", r);
464464
return r;

‎drivers/counter/counter_sam_tc.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ static int counter_sam_initialize(const struct device *dev)
325325

326326
/* Enable channel's clock */
327327
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
328-
(clock_control_subsys_t *)&dev_cfg->clock_cfg[dev_cfg->tc_chan_num]);
328+
(clock_control_subsys_t)&dev_cfg->clock_cfg[dev_cfg->tc_chan_num]);
329329

330330
/* Clock and Mode Selection */
331331
tc_ch->TC_CMR = dev_cfg->reg_cmr;

‎drivers/counter/timer_dtmr_cmsdk_apb.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -155,9 +155,9 @@ static int dtmr_cmsdk_apb_init(const struct device *dev)
155155
}
156156

157157
#ifdef CONFIG_SOC_SERIES_BEETLE
158-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_as);
159-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_ss);
160-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_dss);
158+
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_as);
159+
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_ss);
160+
clock_control_on(clk, (clock_control_subsys_t) &cfg->dtimer_cc_dss);
161161
#endif /* CONFIG_SOC_SERIES_BEETLE */
162162
#endif /* CONFIG_CLOCK_CONTROL */
163163

‎drivers/counter/timer_tmr_cmsdk_apb.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -155,9 +155,9 @@ static int tmr_cmsdk_apb_init(const struct device *dev)
155155
}
156156

157157
#ifdef CONFIG_SOC_SERIES_BEETLE
158-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as);
159-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss);
160-
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss);
158+
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_as);
159+
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_ss);
160+
clock_control_on(clk, (clock_control_subsys_t) &cfg->timer_cc_dss);
161161
#endif /* CONFIG_SOC_SERIES_BEETLE */
162162
#endif /* CONFIG_CLOCK_CONTROL */
163163

‎drivers/crypto/crypto_stm32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ static int crypto_stm32_init(const struct device *dev)
458458
return -ENODEV;
459459
}
460460

461-
if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
461+
if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) {
462462
LOG_ERR("clock op failed\n");
463463
return -EIO;
464464
}

‎drivers/dac/dac_esp32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ static int dac_esp32_init(const struct device *dev)
6666
}
6767

6868
if (clock_control_on(cfg->clock_dev,
69-
(clock_control_subsys_t *) &cfg->clock_subsys) != 0) {
69+
(clock_control_subsys_t) &cfg->clock_subsys) != 0) {
7070
LOG_ERR("DAC clock setup failed (%d)", -EIO);
7171
return -EIO;
7272
}

‎drivers/dac/dac_gd32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ static int dac_gd32_init(const struct device *dev)
156156
}
157157

158158
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
159-
(clock_control_subsys_t *)&cfg->clkid);
159+
(clock_control_subsys_t)&cfg->clkid);
160160

161161
(void)reset_line_toggle_dt(&cfg->reset);
162162

‎drivers/dac/dac_sam.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ static int dac_sam_init(const struct device *dev)
135135

136136
/* Enable DAC clock in PMC */
137137
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
138-
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
138+
(clock_control_subsys_t)&dev_cfg->clock_cfg);
139139

140140
retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
141141
if (retval < 0) {

‎drivers/dac/dac_stm32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,7 @@ static int dac_stm32_init(const struct device *dev)
127127
}
128128

129129
if (clock_control_on(clk,
130-
(clock_control_subsys_t *) &cfg->pclken) != 0) {
130+
(clock_control_subsys_t) &cfg->pclken) != 0) {
131131
return -EIO;
132132
}
133133

‎drivers/disk/sdmmc_stm32.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
139139

140140
if (DT_INST_NUM_CLOCKS(0) > 1) {
141141
if (clock_control_configure(clock,
142-
(clock_control_subsys_t *)&priv->pclken[1],
142+
(clock_control_subsys_t)&priv->pclken[1],
143143
NULL) != 0) {
144144
LOG_ERR("Failed to enable SDMMC domain clock");
145145
return -EIO;
@@ -150,7 +150,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
150150
uint32_t sdmmc_clock_rate;
151151

152152
if (clock_control_get_rate(clock,
153-
(clock_control_subsys_t *)&priv->pclken[1],
153+
(clock_control_subsys_t)&priv->pclken[1],
154154
&sdmmc_clock_rate) != 0) {
155155
LOG_ERR("Failed to get SDMMC domain clock rate");
156156
return -EIO;
@@ -163,7 +163,7 @@ static int stm32_sdmmc_clock_enable(struct stm32_sdmmc_priv *priv)
163163
}
164164

165165
/* Enable the APB clock for stm32_sdmmc */
166-
return clock_control_on(clock, (clock_control_subsys_t *)&priv->pclken[0]);
166+
return clock_control_on(clock, (clock_control_subsys_t)&priv->pclken[0]);
167167
}
168168

169169
static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
@@ -173,7 +173,7 @@ static int stm32_sdmmc_clock_disable(struct stm32_sdmmc_priv *priv)
173173
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
174174

175175
return clock_control_off(clock,
176-
(clock_control_subsys_t *)&priv->pclken);
176+
(clock_control_subsys_t)&priv->pclken);
177177
}
178178

179179
#if STM32_SDMMC_USE_DMA

‎drivers/dma/dma_gd32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -602,7 +602,7 @@ static int dma_gd32_init(const struct device *dev)
602602
const struct dma_gd32_config *cfg = dev->config;
603603

604604
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
605-
(clock_control_subsys_t *)&cfg->clkid);
605+
(clock_control_subsys_t)&cfg->clkid);
606606

607607
#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
608608
(void)reset_line_toggle_dt(&cfg->reset);

‎drivers/dma/dma_sam_xdmac.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ static int sam_xdmac_initialize(const struct device *dev)
360360

361361
/* Enable XDMAC clock in PMC */
362362
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
363-
(clock_control_subsys_t *)&dev_cfg->clock_cfg);
363+
(clock_control_subsys_t)&dev_cfg->clock_cfg);
364364

365365
/* Disable all channels */
366366
xdmac->XDMAC_GD = UINT32_MAX;

‎drivers/dma/dma_stm32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -635,7 +635,7 @@ static int dma_stm32_init(const struct device *dev)
635635
}
636636

637637
if (clock_control_on(clk,
638-
(clock_control_subsys_t *) &config->pclken) != 0) {
638+
(clock_control_subsys_t) &config->pclken) != 0) {
639639
LOG_ERR("clock op failed\n");
640640
return -EIO;
641641
}

‎drivers/dma/dma_stm32_bdma.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,7 @@ static int bdma_stm32_init(const struct device *dev)
786786
}
787787

788788
if (clock_control_on(clk,
789-
(clock_control_subsys_t *) &config->pclken) != 0) {
789+
(clock_control_subsys_t) &config->pclken) != 0) {
790790
LOG_ERR("clock op failed\n");
791791
return -EIO;
792792
}

‎drivers/dma/dma_stm32u5.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -647,7 +647,7 @@ static int dma_stm32_init(const struct device *dev)
647647
const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
648648

649649
if (clock_control_on(clk,
650-
(clock_control_subsys_t *) &config->pclken) != 0) {
650+
(clock_control_subsys_t) &config->pclken) != 0) {
651651
LOG_ERR("clock op failed\n");
652652
return -EIO;
653653
}

‎drivers/dma/dmamux_stm32.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@ static int dmamux_stm32_init(const struct device *dev)
287287
}
288288

289289
if (clock_control_on(clk,
290-
(clock_control_subsys_t *) &config->pclken) != 0) {
290+
(clock_control_subsys_t) &config->pclken) != 0) {
291291
LOG_ERR("clock op failed\n");
292292
return -EIO;
293293
}

‎drivers/entropy/entropy_sam.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,7 @@ static int entropy_sam_init(const struct device *dev)
170170
/* Enable TRNG in PMC */
171171
const struct atmel_sam_pmc_config clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0);
172172
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
173-
(clock_control_subsys_t *)&clock_cfg);
173+
(clock_control_subsys_t)&clock_cfg);
174174

175175
/* Enable the TRNG */
176176
trng->TRNG_CR = TRNG_CR_KEY_PASSWD | TRNG_CR_ENABLE;

‎drivers/entropy/entropy_stm32.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -590,13 +590,13 @@ static int entropy_stm32_rng_init(const struct device *dev)
590590
}
591591

592592
res = clock_control_on(dev_data->clock,
593-
(clock_control_subsys_t *)&dev_cfg->pclken[0]);
593+
(clock_control_subsys_t)&dev_cfg->pclken[0]);
594594
__ASSERT_NO_MSG(res == 0);
595595

596596
/* Configure domain clock if any */
597597
if (DT_INST_NUM_CLOCKS(0) > 1) {
598598
res = clock_control_configure(dev_data->clock,
599-
(clock_control_subsys_t *)&dev_cfg->pclken[1],
599+
(clock_control_subsys_t)&dev_cfg->pclken[1],
600600
NULL);
601601
__ASSERT(res == 0, "Could not select RNG domain clock");
602602
}

‎drivers/espi/espi_npcx.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1207,7 +1207,7 @@ static int espi_npcx_init(const struct device *dev)
12071207
}
12081208

12091209
/* Turn on eSPI device clock first */
1210-
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
1210+
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
12111211
&config->clk_cfg);
12121212
if (ret < 0) {
12131213
LOG_ERR("Turn on eSPI clock fail %d", ret);

‎drivers/espi/host_subs_npcx.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1090,7 +1090,7 @@ int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
10901090
return -ENODEV;
10911091
}
10921092

1093-
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
1093+
ret = clock_control_on(clk_dev, (clock_control_subsys_t)
10941094
&host_sub_cfg.clks_list[i]);
10951095
if (ret < 0) {
10961096
return ret;

‎drivers/ethernet/eth_dwmac_stm32h7x.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,9 @@ int dwmac_bus_init(struct dwmac_priv *p)
5757
return -ENODEV;
5858
}
5959

60-
ret = clock_control_on(p->clock, (clock_control_subsys_t *)&pclken);
61-
ret |= clock_control_on(p->clock, (clock_control_subsys_t *)&pclken_tx);
62-
ret |= clock_control_on(p->clock, (clock_control_subsys_t *)&pclken_rx);
60+
ret = clock_control_on(p->clock, (clock_control_subsys_t)&pclken);
61+
ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_tx);
62+
ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_rx);
6363
if (ret) {
6464
LOG_ERR("Failed to enable ethernet clock");
6565
return -EIO;

‎drivers/ethernet/eth_sam_gmac.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1779,7 +1779,7 @@ static int eth_initialize(const struct device *dev)
17791779
#ifdef CONFIG_SOC_FAMILY_SAM
17801780
/* Enable GMAC module's clock */
17811781
(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
1782-
(clock_control_subsys_t *)&cfg->clock_cfg);
1782+
(clock_control_subsys_t)&cfg->clock_cfg);
17831783
#else
17841784
/* Enable MCLK clock on GMAC */
17851785
MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;

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