net: convert to using newly introduced integer sized types

Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837
Signed-off-by: Kumar Gala <[email protected]>

Author: galak

drivers/ethernet/eth_dw.c

@@ -23,23 +23,23 @@
 #define SYS_LOG_LEVEL CONFIG_SYS_LOG_ETHERNET_LEVEL
 #include <logging/sys_log.h>
 
-static inline uint32_t eth_read(uint32_t base_addr, uint32_t offset)
+static inline u32_t eth_read(u32_t base_addr, u32_t offset)
 {
 	return sys_read32(base_addr + offset);
 }
 
-static inline void eth_write(uint32_t base_addr, uint32_t offset,
-			     uint32_t val)
+static inline void eth_write(u32_t base_addr, u32_t offset,
+			     u32_t val)
 {
 	sys_write32(val, base_addr + offset);
 }
 
 static void eth_rx(struct device *port)
 {
 	struct eth_runtime *context = port->driver_data;
-	uint32_t base_addr = context->base_addr;
+	u32_t base_addr = context->base_addr;
 	struct net_buf *buf;
-	uint32_t frm_len = 0;
+	u32_t frm_len = 0;
 
 	/* Check whether the RX descriptor is still owned by the device.  If not,
 	 * process the received frame or an error that may have occurred.
@@ -97,7 +97,7 @@ static void eth_rx(struct device *port)
 static int eth_tx(struct device *port, struct net_buf *buf)
 {
 	struct eth_runtime *context = port->driver_data;
-	uint32_t base_addr = context->base_addr;
+	u32_t base_addr = context->base_addr;
 
 	/* Wait until the TX descriptor is no longer owned by the device. */
 	while (context->tx_desc.own == 1) {
@@ -135,8 +135,8 @@ static int eth_tx(struct device *port, struct net_buf *buf)
 static void eth_dw_isr(struct device *port)
 {
 	struct eth_runtime *context = port->driver_data;
-	uint32_t base_addr = context->base_addr;
-	uint32_t int_status;
+	u32_t base_addr = context->base_addr;
+	u32_t int_status;
 
 	int_status = eth_read(base_addr, REG_ADDR_STATUS);
 
@@ -186,14 +186,14 @@ static int eth_initialize(struct device *port)
 {
 	struct eth_runtime *context = port->driver_data;
 	const struct eth_config *config = port->config->config_info;
-	uint32_t base_addr;
+	u32_t base_addr;
 
 	union {
 		struct {
-			uint8_t bytes[6];
-			uint8_t pad[2];
+			u8_t bytes[6];
+			u8_t pad[2];
 		} __attribute__((packed));
-		uint32_t words[2];
+		u32_t words[2];
 	} mac_addr;
 
 	if (!eth_setup(port))
@@ -214,7 +214,7 @@ static int eth_initialize(struct device *port)
 	context->tx_desc.tdes0 = 0;
 	context->tx_desc.tdes1 = 0;
 
-	context->tx_desc.buf1_ptr = (uint8_t *)context->tx_buf;
+	context->tx_desc.buf1_ptr = (u8_t *)context->tx_buf;
 	context->tx_desc.tx_end_of_ring = 1;
 	context->tx_desc.first_seg_in_frm = 1;
 	context->tx_desc.last_seg_in_frm = 1;
@@ -224,16 +224,16 @@ static int eth_initialize(struct device *port)
 	context->rx_desc.rdes0 = 0;
 	context->rx_desc.rdes1 = 0;
 
-	context->rx_desc.buf1_ptr = (uint8_t *)context->rx_buf;
+	context->rx_desc.buf1_ptr = (u8_t *)context->rx_buf;
 	context->rx_desc.own = 1;
 	context->rx_desc.first_desc = 1;
 	context->rx_desc.last_desc = 1;
 	context->rx_desc.rx_buf1_sz = UIP_BUFSIZE;
 	context->rx_desc.rx_end_of_ring = 1;
 
 	/* Install transmit and receive descriptors. */
-	eth_write(base_addr, REG_ADDR_RX_DESC_LIST, (uint32_t)&context->rx_desc);
-	eth_write(base_addr, REG_ADDR_TX_DESC_LIST, (uint32_t)&context->tx_desc);
+	eth_write(base_addr, REG_ADDR_RX_DESC_LIST, (u32_t)&context->rx_desc);
+	eth_write(base_addr, REG_ADDR_TX_DESC_LIST, (u32_t)&context->tx_desc);
 
 	eth_write(base_addr, REG_ADDR_MAC_CONF,
 		  /* Set the RMII speed to 100Mbps */

drivers/ethernet/eth_dw_priv.h

@@ -23,7 +23,7 @@ extern "C" {
 typedef void (*eth_config_irq_t)(struct device *port);
 
 struct eth_config {
-	uint32_t irq_num;
+	u32_t irq_num;
 	eth_config_irq_t config_func;
 
 #ifdef CONFIG_ETH_DW_SHARED_IRQ
@@ -46,118 +46,118 @@ struct eth_tx_desc {
 	union {
 		struct {
 			/* Only valid in half-duplex mode. */
-			uint32_t deferred_bit      : 1;
-			uint32_t err_underflow     : 1;
-			uint32_t err_excess_defer  : 1;
-			uint32_t coll_cnt_slot_num : 4;
-			uint32_t vlan_frm          : 1;
-			uint32_t err_excess_coll   : 1;
-			uint32_t err_late_coll     : 1;
-			uint32_t err_no_carrier    : 1;
-			uint32_t err_carrier_loss  : 1;
-			uint32_t err_ip_payload    : 1;
-			uint32_t err_frm_flushed   : 1;
-			uint32_t err_jabber_tout   : 1;
+			u32_t deferred_bit      : 1;
+			u32_t err_underflow     : 1;
+			u32_t err_excess_defer  : 1;
+			u32_t coll_cnt_slot_num : 4;
+			u32_t vlan_frm          : 1;
+			u32_t err_excess_coll   : 1;
+			u32_t err_late_coll     : 1;
+			u32_t err_no_carrier    : 1;
+			u32_t err_carrier_loss  : 1;
+			u32_t err_ip_payload    : 1;
+			u32_t err_frm_flushed   : 1;
+			u32_t err_jabber_tout   : 1;
 			/* OR of all other error bits. */
-			uint32_t err_summary       : 1;
-			uint32_t err_ip_hdr        : 1;
-			uint32_t tx_timestamp_stat : 1;
-			uint32_t vlan_ins_ctrl     : 2;
-			uint32_t addr2_chained     : 1;
-			uint32_t tx_end_of_ring    : 1;
-			uint32_t chksum_ins_ctrl   : 2;
-			uint32_t replace_crc       : 1;
-			uint32_t tx_timestamp_en   : 1;
-			uint32_t dis_pad           : 1;
-			uint32_t dis_crc           : 1;
-			uint32_t first_seg_in_frm  : 1;
-			uint32_t last_seg_in_frm   : 1;
-			uint32_t intr_on_complete  : 1;
+			u32_t err_summary       : 1;
+			u32_t err_ip_hdr        : 1;
+			u32_t tx_timestamp_stat : 1;
+			u32_t vlan_ins_ctrl     : 2;
+			u32_t addr2_chained     : 1;
+			u32_t tx_end_of_ring    : 1;
+			u32_t chksum_ins_ctrl   : 2;
+			u32_t replace_crc       : 1;
+			u32_t tx_timestamp_en   : 1;
+			u32_t dis_pad           : 1;
+			u32_t dis_crc           : 1;
+			u32_t first_seg_in_frm  : 1;
+			u32_t last_seg_in_frm   : 1;
+			u32_t intr_on_complete  : 1;
 			/* When set, descriptor is owned by DMA. */
-			uint32_t own               : 1;
+			u32_t own               : 1;
 		};
-		uint32_t tdes0;
+		u32_t tdes0;
 	};
 	/* Second word of transmit descriptor */
 	union {
 		struct {
-			uint32_t tx_buf1_sz        : 13;
-			uint32_t                   : 3;
-			uint32_t tx_buf2_sz        : 13;
-			uint32_t src_addr_ins_ctrl : 3;
+			u32_t tx_buf1_sz        : 13;
+			u32_t                   : 3;
+			u32_t tx_buf2_sz        : 13;
+			u32_t src_addr_ins_ctrl : 3;
 		};
-		uint32_t tdes1;
+		u32_t tdes1;
 	};
 	/* Pointer to frame data buffer */
-	uint8_t *buf1_ptr;
+	u8_t *buf1_ptr;
 	/* Unused, since this driver initializes only a single descriptor for each
 	 * direction.
 	 */
-	uint8_t *buf2_ptr;
+	u8_t *buf2_ptr;
 };
 
 /* Transmit descriptor */
 struct eth_rx_desc {
 	/* First word of receive descriptor */
 	union {
 		struct {
-			uint32_t ext_stat          : 1;
-			uint32_t err_crc           : 1;
-			uint32_t err_dribble_bit   : 1;
-			uint32_t err_rx_mii        : 1;
-			uint32_t err_rx_wdt        : 1;
-			uint32_t frm_type          : 1;
-			uint32_t err_late_coll     : 1;
-			uint32_t giant_frm         : 1;
-			uint32_t last_desc         : 1;
-			uint32_t first_desc        : 1;
-			uint32_t vlan_tag          : 1;
-			uint32_t err_overflow      : 1;
-			uint32_t length_err        : 1;
-			uint32_t s_addr_filt_fail  : 1;
-			uint32_t err_desc          : 1;
-			uint32_t err_summary       : 1;
-			uint32_t frm_len           : 14;
-			uint32_t d_addr_filt_fail  : 1;
-			uint32_t own               : 1;
+			u32_t ext_stat          : 1;
+			u32_t err_crc           : 1;
+			u32_t err_dribble_bit   : 1;
+			u32_t err_rx_mii        : 1;
+			u32_t err_rx_wdt        : 1;
+			u32_t frm_type          : 1;
+			u32_t err_late_coll     : 1;
+			u32_t giant_frm         : 1;
+			u32_t last_desc         : 1;
+			u32_t first_desc        : 1;
+			u32_t vlan_tag          : 1;
+			u32_t err_overflow      : 1;
+			u32_t length_err        : 1;
+			u32_t s_addr_filt_fail  : 1;
+			u32_t err_desc          : 1;
+			u32_t err_summary       : 1;
+			u32_t frm_len           : 14;
+			u32_t d_addr_filt_fail  : 1;
+			u32_t own               : 1;
 		};
-		uint32_t rdes0;
+		u32_t rdes0;
 	};
 	/* Second word of receive descriptor */
 	union {
 		struct {
-			uint32_t rx_buf1_sz        : 13;
-			uint32_t                   : 1;
-			uint32_t addr2_chained     : 1;
-			uint32_t rx_end_of_ring    : 1;
-			uint32_t rx_buf2_sz        : 13;
-			uint32_t                   : 2;
-			uint32_t dis_int_compl     : 1;
+			u32_t rx_buf1_sz        : 13;
+			u32_t                   : 1;
+			u32_t addr2_chained     : 1;
+			u32_t rx_end_of_ring    : 1;
+			u32_t rx_buf2_sz        : 13;
+			u32_t                   : 2;
+			u32_t dis_int_compl     : 1;
 		};
-		uint32_t rdes1;
+		u32_t rdes1;
 	};
 	/* Pointer to frame data buffer */
-	uint8_t *buf1_ptr;
+	u8_t *buf1_ptr;
 	/* Unused, since this driver initializes only a single descriptor for each
 	 * direction.
 	 */
-	uint8_t *buf2_ptr;
+	u8_t *buf2_ptr;
 };
 
 /* Driver metadata associated with each Ethernet device */
 struct eth_runtime {
-	uint32_t base_addr;
+	u32_t base_addr;
 #ifdef CONFIG_PCI
 	struct pci_dev_info pci_dev;
 #endif  /* CONFIG_PCI */
 	/* Transmit descriptor */
 	volatile struct eth_tx_desc tx_desc;
 	/* Transmit DMA packet buffer */
-	volatile uint8_t tx_buf[UIP_BUFSIZE];
+	volatile u8_t tx_buf[UIP_BUFSIZE];
 	/* Receive descriptor */
 	volatile struct eth_rx_desc rx_desc;
 	/* Receive DMA packet buffer */
-	volatile uint8_t rx_buf[UIP_BUFSIZE];
+	volatile u8_t rx_buf[UIP_BUFSIZE];
 };
 
 #define MMC_DEFAULT_MASK               0xffffffff