boards: mimxrt1160_evk: Enable ENET

Enable 10/100M Ethernet for RT1160 EVK

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

boards/arm/mimxrt1160_evk/Kconfig.defconfig

@@ -34,4 +34,11 @@ endchoice
 
 endif #FLASH
 
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
+
+endif # NETWORKING
+
 endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4

boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts

@@ -114,3 +114,10 @@
 &edma0 {
 	status = "okay";
 };
+
+&enet {
+	status = "okay";
+	ptp {
+		status = "okay";
+	};
+};

boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml

@@ -23,3 +23,4 @@ supported:
   - i2c
   - pwm
   - dma
+  - netif:eth

boards/arm/mimxrt1160_evk/pinmux.c

@@ -12,6 +12,14 @@
 
 LOG_MODULE_REGISTER(mimxrt1160_evk, LOG_LEVEL_INF);
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+static gpio_pin_config_t enet_gpio_config = {
+	.direction = kGPIO_DigitalOutput,
+	.outputLogic = 0,
+	.interruptMode = kGPIO_NoIntmode
+};
+#endif
+
 static int mimxrt1160_evk_init(const struct device *dev)
 {
 	ARG_UNUSED(dev);
@@ -94,7 +102,63 @@ static int mimxrt1160_evk_init(const struct device *dev)
 	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, 0x0AU);
 	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, 0x0AU);
 #endif
+
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_12_GPIO9_IO11, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_ENET_MDC, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_33_ENET_MDIO, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0U);
+	IOMUXC_GPR->GPR4 = ((IOMUXC_GPR->GPR4 &
+		(~(IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK))) |
+			IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U));
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_12_GPIO12_IO12, 0U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_12_GPIO9_IO11, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 0x03U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_LPSR_12_GPIO12_IO12, 0x0EU);
+
+	/* Initialize ENET_INT GPIO */
+	GPIO_PinInit(GPIO9, 11, &enet_gpio_config);
+	GPIO_PinInit(GPIO12, 12, &enet_gpio_config);
+
+	/* pull up the ENET_INT before RESET. */
+	GPIO_WritePinOutput(GPIO9, 11, 1);
+	GPIO_WritePinOutput(GPIO12, 12, 0);
+
+	/* 50M ENET_REF_CLOCK output to PHY and ENET module. */
+	IOMUXC_GPR->GPR4 |= 0x3;
+#endif
+
 	return 0;
 }
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+static int mimxrt1170_evk_phy_reset(const struct device *dev)
+{
+	/* RESET PHY chip. */
+	k_busy_wait(USEC_PER_MSEC * 10U);
+	GPIO_WritePinOutput(GPIO12, 12, 1);
+
+	return 0;
+}
+#endif
+
 SYS_INIT(mimxrt1160_evk_init, PRE_KERNEL_1, 0);
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+SYS_INIT(mimxrt1170_evk_phy_reset, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY);
+#endif

dts/arm/nxp/nxp_rt1160_cm7.dtsi

@@ -29,11 +29,13 @@
 			itcm: itcm@0 {
 				compatible = "nxp,imx-itcm";
 				reg = <0x00000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "ITCM";
 			};
 
 			dtcm: dtcm@20000000 {
 				compatible = "nxp,imx-dtcm";
 				reg = <0x20000000 DT_SIZE_K(256)>;
+				zephyr,memory-region = "DTCM";
 			};
 		};