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carlocaionenashif
carlocaione
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nashif
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barriers: Move __DSB() to the new API
Remove the arch-specific ARM-centric __DSB() macro and use the new barrier API instead. Signed-off-by: Carlo Caione <[email protected]>
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55 files changed

+157
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‎arch/arm/core/aarch32/cortex_a_r/cache.c

+3-2
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <zephyr/kernel.h>
1616
#include <zephyr/cache.h>
1717
#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
18+
#include <zephyr/sys/barrier.h>
1819

1920
/* Cache Type Register */
2021
#define CTR_DMINLINE_SHIFT 16
@@ -51,7 +52,7 @@ void arch_dcache_enable(void)
5152

5253
val = __get_SCTLR();
5354
val |= SCTLR_C_Msk;
54-
__DSB();
55+
barrier_dsync_fence_full();
5556
__set_SCTLR(val);
5657
__ISB();
5758
}
@@ -62,7 +63,7 @@ void arch_dcache_disable(void)
6263

6364
val = __get_SCTLR();
6465
val &= ~SCTLR_C_Msk;
65-
__DSB();
66+
barrier_dsync_fence_full();
6667
__set_SCTLR(val);
6768
__ISB();
6869

‎arch/arm/core/aarch32/cortex_m/fault.c

+3-2
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include <inttypes.h>
1818
#include <zephyr/exc_handle.h>
1919
#include <zephyr/logging/log.h>
20+
#include <zephyr/sys/barrier.h>
2021
LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
2122

2223
#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
@@ -710,13 +711,13 @@ static inline bool z_arm_is_synchronous_svc(z_arch_esf_t *esf)
710711
uint16_t fault_insn = *(ret_addr - 1);
711712
#else
712713
SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
713-
__DSB();
714+
barrier_dsync_fence_full();
714715
__ISB();
715716

716717
uint16_t fault_insn = *(ret_addr - 1);
717718

718719
SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
719-
__DSB();
720+
barrier_dsync_fence_full();
720721
__ISB();
721722
#endif /* ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE */
722723

‎arch/arm/core/aarch32/cortex_m/scb.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include <zephyr/kernel.h>
1818
#include <zephyr/arch/cpu.h>
1919
#include <zephyr/sys/util.h>
20+
#include <zephyr/sys/barrier.h>
2021
#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
2122
#include <zephyr/linker/linker-defs.h>
2223
#include <zephyr/cache.h>
@@ -132,7 +133,7 @@ void z_arm_init_arch_hw_at_boot(void)
132133
/* Restore Interrupts */
133134
__enable_irq();
134135

135-
__DSB();
136+
barrier_dsync_fence_full();
136137
__ISB();
137138
}
138139
#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

‎arch/arm/core/aarch32/irq_manage.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#include <zephyr/drivers/interrupt_controller/gic.h>
2424
#endif
2525
#include <zephyr/sys/__assert.h>
26+
#include <zephyr/sys/barrier.h>
2627
#include <zephyr/toolchain.h>
2728
#include <zephyr/linker/sections.h>
2829
#include <zephyr/sw_isr_table.h>
@@ -281,7 +282,7 @@ void irq_target_state_set_all_non_secure(void)
281282
NVIC->ICER[i] = 0xFFFFFFFF;
282283
}
283284

284-
__DSB();
285+
barrier_dsync_fence_full();
285286
__ISB();
286287

287288
/* Set all NVIC interrupt lines to target Non-Secure */

‎arch/arm/core/aarch32/mmu/arm_mmu.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
#include <zephyr/sys/__assert.h>
2828
#include <zephyr/sys/util.h>
2929
#include <zephyr/sys/mem_manage.h>
30+
#include <zephyr/sys/barrier.h>
3031

3132
#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
3233

@@ -115,7 +116,7 @@ static void arm_mmu_l2_map_page(uint32_t va, uint32_t pa,
115116
static void invalidate_tlb_all(void)
116117
{
117118
__set_TLBIALL(0); /* 0 = opc2 = invalidate entire TLB */
118-
__DSB();
119+
barrier_dsync_fence_full();
119120
__ISB();
120121
}
121122

‎arch/arm/core/aarch32/mpu/arm_mpu.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ void arm_core_mpu_enable(void)
152152
__set_SCTLR(val);
153153

154154
/* Make sure that all the registers are set before proceeding */
155-
__DSB();
155+
barrier_dsync_fence_full();
156156
__ISB();
157157
}
158158

@@ -164,14 +164,14 @@ void arm_core_mpu_disable(void)
164164
uint32_t val;
165165

166166
/* Force any outstanding transfers to complete before disabling MPU */
167-
__DSB();
167+
barrier_dsync_fence_full();
168168

169169
val = __get_SCTLR();
170170
val &= ~SCTLR_MPU_ENABLE;
171171
__set_SCTLR(val);
172172

173173
/* Make sure that all the registers are set before proceeding */
174-
__DSB();
174+
barrier_dsync_fence_full();
175175
__ISB();
176176
}
177177
#else
@@ -190,7 +190,7 @@ void arm_core_mpu_enable(void)
190190
#endif
191191

192192
/* Make sure that all the registers are set before proceeding */
193-
__DSB();
193+
barrier_dsync_fence_full();
194194
__ISB();
195195
}
196196

‎arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h

+5-4
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
1313
#include <zephyr/logging/log.h>
1414
#include <zephyr/sys/math_extras.h>
15+
#include <zephyr/sys/barrier.h>
1516

1617
/**
1718
* @brief internal structure holding information of
@@ -79,20 +80,20 @@ static inline void mpu_clear_region(uint32_t rnr)
7980
static inline void mpu_set_mair0(uint32_t mair0)
8081
{
8182
write_mair0(mair0);
82-
__DSB();
83+
barrier_dsync_fence_full();
8384
__ISB();
8485
}
8586

8687
static inline void mpu_set_rnr(uint32_t rnr)
8788
{
8889
write_prselr(rnr);
89-
__DSB();
90+
barrier_dsync_fence_full();
9091
}
9192

9293
static inline void mpu_set_rbar(uint32_t rbar)
9394
{
9495
write_prbar(rbar);
95-
__DSB();
96+
barrier_dsync_fence_full();
9697
__ISB();
9798
}
9899

@@ -104,7 +105,7 @@ static inline uint32_t mpu_get_rbar(void)
104105
static inline void mpu_set_rlar(uint32_t rlar)
105106
{
106107
write_prlar(rlar);
107-
__DSB();
108+
barrier_dsync_fence_full();
108109
__ISB();
109110
}
110111

‎arch/arm/core/aarch32/mpu/nxp_mpu.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -399,7 +399,7 @@ void arm_core_mpu_enable(void)
399399
SYSMPU->CESR |= SYSMPU_CESR_VLD_MASK;
400400

401401
/* Make sure that all the registers are set before proceeding */
402-
__DSB();
402+
barrier_dsync_fence_full();
403403
__ISB();
404404
}
405405

‎arch/arm/core/aarch32/prep_c.c

+3-2
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include <zephyr/kernel.h>
2020
#include <kernel_internal.h>
2121
#include <zephyr/linker/linker-defs.h>
22+
#include <zephyr/sys/barrier.h>
2223

2324
#if !defined(CONFIG_CPU_CORTEX_M)
2425
#include <zephyr/arch/arm/aarch32/cortex_a_r/lib_helpers.h>
@@ -53,7 +54,7 @@ void *_vector_table_pointer;
5354
static inline void relocate_vector_table(void)
5455
{
5556
SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
56-
__DSB();
57+
barrier_dsync_fence_full();
5758
__ISB();
5859
}
5960

@@ -149,7 +150,7 @@ static inline void z_arm_floating_point_init(void)
149150
/* Make the side-effects of modifying the FPCCR be realized
150151
* immediately.
151152
*/
152-
__DSB();
153+
barrier_dsync_fence_full();
153154
__ISB();
154155

155156
/* Initialize the Floating Point Status and Control Register. */

‎arch/arm64/core/cortex_r/arm_mpu.c

+5-5
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ void arm_core_mpu_enable(void)
7676
val = read_sctlr_el1();
7777
val |= SCTLR_M_BIT;
7878
write_sctlr_el1(val);
79-
dsb();
79+
barrier_dsync_fence_full();
8080
isb();
8181
}
8282

@@ -93,7 +93,7 @@ void arm_core_mpu_disable(void)
9393
val = read_sctlr_el1();
9494
val &= ~SCTLR_M_BIT;
9595
write_sctlr_el1(val);
96-
dsb();
96+
barrier_dsync_fence_full();
9797
isb();
9898
}
9999

@@ -112,18 +112,18 @@ static void mpu_init(void)
112112
uint64_t mair = MPU_MAIR_ATTRS;
113113

114114
write_mair_el1(mair);
115-
dsb();
115+
barrier_dsync_fence_full();
116116
isb();
117117
}
118118

119119
static inline void mpu_set_region(uint32_t rnr, uint64_t rbar,
120120
uint64_t rlar)
121121
{
122122
write_prselr_el1(rnr);
123-
dsb();
123+
barrier_dsync_fence_full();
124124
write_prbar_el1(rbar);
125125
write_prlar_el1(rlar);
126-
dsb();
126+
barrier_dsync_fence_full();
127127
isb();
128128
}
129129

‎arch/arm64/core/fpu.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <zephyr/kernel_structs.h>
1010
#include <kernel_arch_interface.h>
1111
#include <zephyr/arch/cpu.h>
12+
#include <zephyr/sys/barrier.h>
1213

1314
/* to be found in fpu.S */
1415
extern void z_arm64_fpu_save(struct z_arm64_fp_context *saved_fp_context);
@@ -78,7 +79,7 @@ void z_arm64_flush_local_fpu(void)
7879
/* save current owner's content */
7980
z_arm64_fpu_save(&owner->arch.saved_fp_context);
8081
/* make sure content made it to memory before releasing */
81-
dsb();
82+
barrier_dsync_fence_full();
8283
/* release ownership */
8384
_current_cpu->arch.fpu_owner = NULL;
8485
DBG("disable", owner);
@@ -125,7 +126,7 @@ static void flush_owned_fpu(struct k_thread *thread)
125126
if (thread == _current) {
126127
z_arm64_flush_local_fpu();
127128
while (_kernel.cpus[i].arch.fpu_owner == thread) {
128-
dsb();
129+
barrier_dsync_fence_full();
129130
}
130131
}
131132
}
@@ -236,7 +237,7 @@ void z_arm64_fpu_trap(z_arch_esf_t *esf)
236237

237238
if (owner) {
238239
z_arm64_fpu_save(&owner->arch.saved_fp_context);
239-
dsb();
240+
barrier_dsync_fence_full();
240241
_current_cpu->arch.fpu_owner = NULL;
241242
DBG("save", owner);
242243
}

‎arch/arm64/core/smp.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include <zephyr/drivers/interrupt_controller/gic.h>
2323
#include <zephyr/drivers/pm_cpu_ops.h>
2424
#include <zephyr/sys/arch_interface.h>
25+
#include <zephyr/sys/barrier.h>
2526
#include <zephyr/irq.h>
2627
#include "boot.h"
2728

@@ -87,7 +88,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
8788
arm64_cpu_boot_params.arg = arg;
8889
arm64_cpu_boot_params.cpu_num = cpu_num;
8990

90-
dsb();
91+
barrier_dsync_fence_full();
9192

9293
/* store mpid last as this is our synchronization point */
9394
arm64_cpu_boot_params.mpid = cpu_mpid;
@@ -139,15 +140,15 @@ void z_arm64_secondary_start(void)
139140

140141
fn = arm64_cpu_boot_params.fn;
141142
arg = arm64_cpu_boot_params.arg;
142-
dsb();
143+
barrier_dsync_fence_full();
143144

144145
/*
145146
* Secondary core clears .fn to announce its presence.
146147
* Primary core is polling for this. We no longer own
147148
* arm64_cpu_boot_params afterwards.
148149
*/
149150
arm64_cpu_boot_params.fn = NULL;
150-
dsb();
151+
barrier_dsync_fence_full();
151152
sev();
152153

153154
fn(arg);

‎drivers/cache/cache_aspeed.c

+5-4
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <zephyr/kernel.h>
88
#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
99
#include <zephyr/drivers/syscon.h>
10+
#include <zephyr/sys/barrier.h>
1011

1112
/*
1213
* cache area control: each bit controls 32KB cache area
@@ -145,10 +146,10 @@ int cache_data_invd_all(void)
145146
ctrl &= ~DCACHE_CLEAN;
146147
syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
147148

148-
__DSB();
149+
barrier_dsync_fence_full();
149150
ctrl |= DCACHE_CLEAN;
150151
syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
151-
__DSB();
152+
barrier_dsync_fence_full();
152153

153154
/* exit critical section */
154155
if (!k_is_in_isr()) {
@@ -181,7 +182,7 @@ int cache_data_invd_range(void *addr, size_t size)
181182
syscon_write_reg(dev, CACHE_INVALID_REG, DCACHE_INVALID(aligned_addr));
182183
aligned_addr += CACHE_LINE_SIZE;
183184
}
184-
__DSB();
185+
barrier_dsync_fence_full();
185186

186187
/* exit critical section */
187188
if (!k_is_in_isr()) {
@@ -242,7 +243,7 @@ int cache_instr_invd_range(void *addr, size_t size)
242243
syscon_write_reg(dev, CACHE_INVALID_REG, ICACHE_INVALID(aligned_addr));
243244
aligned_addr += CACHE_LINE_SIZE;
244245
}
245-
__DSB();
246+
barrier_dsync_fence_full();
246247

247248
/* exit critical section */
248249
if (!k_is_in_isr()) {

‎drivers/clock_control/clock_control_mchp_xec.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
1616
#include <zephyr/irq.h>
1717
#include <zephyr/logging/log.h>
18+
#include <zephyr/sys/barrier.h>
1819
LOG_MODULE_REGISTER(clock_control_xec, LOG_LEVEL_ERR);
1920

2021
#define CLK32K_SIL_OSC_DELAY 256
@@ -765,7 +766,7 @@ static void xec_clock_control_core_clock_divider_set(uint8_t clkdiv)
765766
arch_nop();
766767
arch_nop();
767768
arch_nop();
768-
__DSB();
769+
barrier_dsync_fence_full();
769770
__ISB();
770771
}
771772

‎drivers/counter/counter_mcux_gpt.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <zephyr/irq.h>
1212
#include <fsl_gpt.h>
1313
#include <zephyr/logging/log.h>
14+
#include <zephyr/sys/barrier.h>
1415

1516
LOG_MODULE_REGISTER(mcux_gpt, CONFIG_COUNTER_LOG_LEVEL);
1617

@@ -114,7 +115,7 @@ void mcux_gpt_isr(const struct device *dev)
114115
status = GPT_GetStatusFlags(config->base, kGPT_OutputCompare1Flag |
115116
kGPT_RollOverFlag);
116117
GPT_ClearStatusFlags(config->base, status);
117-
__DSB();
118+
barrier_dsync_fence_full();
118119

119120
if ((status & kGPT_OutputCompare1Flag) && data->alarm_callback) {
120121
GPT_DisableInterrupts(config->base,

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