From 74e287a7eb13124c3df8ea5239c0737aade1d644 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 3 Jul 2019 21:18:38 -0700 Subject: [PATCH] write_verilog escaped bus port name "input [7:0] \in[0] ;" --- network/ParseBus.cc | 4 +++ network/ParseBus.hh | 6 +++- network/VerilogNamespace.cc | 18 ++++++++--- network/VerilogNamespace.hh | 1 - verilog/Verilog.i | 5 ++- verilog/VerilogReader.cc | 62 ++++++++++++++++++++----------------- verilog/VerilogWriter.cc | 43 +++++++++++++------------ 7 files changed, 83 insertions(+), 56 deletions(-) diff --git a/network/ParseBus.cc b/network/ParseBus.cc index 2652d037..4dfef34e 100644 --- a/network/ParseBus.cc +++ b/network/ParseBus.cc @@ -43,6 +43,7 @@ void parseBusName(const char *name, const char brkt_left, const char brkt_right, + // Return values. char *&bus_name, int &index) { @@ -55,6 +56,7 @@ void parseBusName(const char *name, const char *brkts_left, const char *brkts_right, + // Return values. char *&bus_name, int &index) { @@ -81,6 +83,7 @@ void parseBusRange(const char *name, const char brkt_left, const char brkt_right, + // Return values. char *&bus_name, int &from, int &to) @@ -94,6 +97,7 @@ void parseBusRange(const char *name, const char *brkts_left, const char *brkts_right, + // Return values. char *&bus_name, int &from, int &to) diff --git a/network/ParseBus.hh b/network/ParseBus.hh index 58a76e6a..7d0ad859 100644 --- a/network/ParseBus.hh +++ b/network/ParseBus.hh @@ -27,7 +27,7 @@ isBusName(const char *name, // Parse name as a bus. // signal -// bus_name = 0 +// bus_name = nullptr // bus[bit] // bus_name = "bus" // index = bit @@ -36,6 +36,7 @@ void parseBusName(const char *name, const char brkt_left, const char brkt_right, + // Return values. char *&bus_name, int &index); // Allow multiple different left/right bus brackets. @@ -43,6 +44,7 @@ void parseBusName(const char *name, const char *brkts_left, const char *brkts_right, + // Return values. char *&bus_name, int &index); @@ -53,6 +55,7 @@ void parseBusRange(const char *name, const char brkt_left, const char brkt_right, + // Return values. char *&bus_name, int &from, int &to); @@ -62,6 +65,7 @@ void parseBusRange(const char *name, const char *brkts_left, const char *brkts_right, + // Return values. char *&bus_name, int &from, int &to); diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc index f3133d99..170dda4a 100644 --- a/network/VerilogNamespace.cc +++ b/network/VerilogNamespace.cc @@ -17,6 +17,7 @@ #include #include "Machine.hh" #include "StringUtil.hh" +#include "ParseBus.hh" #include "VerilogNamespace.hh" namespace sta { @@ -25,21 +26,29 @@ const char * instanceVerilogName(const char *sta_name, const char escape) { - return staToVerilog(sta_name, true, escape); + return staToVerilog(sta_name, escape); } const char * netVerilogName(const char *sta_name, const char escape) { - return staToVerilog(sta_name, false, escape); + char *bus_name; + int index; + parseBusName(sta_name, '[', ']', bus_name, index); + if (bus_name) + return stringPrintTmp("%s[%d]", + staToVerilog(bus_name, escape), + index); + else + return staToVerilog(sta_name, escape); } const char * portVerilogName(const char *sta_name, const char escape) { - return staToVerilog(sta_name, false, escape); + return staToVerilog(sta_name, escape); } // Append ch to str at insert. Resize str if necessary. @@ -63,7 +72,6 @@ vstringAppend(char *&str, const char * staToVerilog(const char *sta_name, - bool escape_brkts, const char escape) { const char bus_brkt_left = '['; @@ -93,7 +101,7 @@ staToVerilog(const char *sta_name, else { bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right); if ((!(isalnum(ch) || ch == '_') && !is_brkt) - || (is_brkt && escape_brkts)) + || is_brkt) escaped = true; vstringAppend(verilog_name, verilog_name_end, v, ch); } diff --git a/network/VerilogNamespace.hh b/network/VerilogNamespace.hh index 7f9cfe66..dec08f76 100644 --- a/network/VerilogNamespace.hh +++ b/network/VerilogNamespace.hh @@ -21,7 +21,6 @@ namespace sta { const char * staToVerilog(const char *sta_name, - bool escape_brkts, const char escape); const char * verilogToSta(const char *verilog_name); diff --git a/verilog/Verilog.i b/verilog/Verilog.i index 970f42a8..d61f7a54 100644 --- a/verilog/Verilog.i +++ b/verilog/Verilog.i @@ -53,7 +53,10 @@ void write_verilog_cmd(const char *filename, bool sort) { - Network *network = cmdNetwork(); + // This does NOT want the SDC (cmd) network because it wants + // to see the sta internal names. + Sta *sta = Sta::sta(); + Network *network = sta->network(); writeVerilog(filename, sort, network); } diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc index bc5e884b..b1dc4c2e 100644 --- a/verilog/VerilogReader.cc +++ b/verilog/VerilogReader.cc @@ -1721,38 +1721,44 @@ VerilogReader::linkNetwork(const char *top_cell_name, bool make_black_boxes, Report *report) { - Cell *top_cell = network_->findCell(library_, top_cell_name); - VerilogModule *module = verilog_reader->module(top_cell); - if (module) { - // Seed the recursion for expansion with the top level instance. - Instance *top_instance = network_->makeInstance(top_cell, "", nullptr); - VerilogBindingTbl bindings(zero_net_name_, one_net_name_); - VerilogNetSeq::Iterator port_iter(module->ports()); - while (port_iter.hasNext()) { - VerilogNet *mod_port = port_iter.next(); - VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module, - this); - while (net_name_iter->hasNext()) { - const char *net_name = net_name_iter->next(); - Port *port = network_->findPort(top_cell, net_name); - Net *net = bindings.ensureNetBinding(net_name, top_instance, network_); - // Guard against repeated port name. - if (network_->findPin(top_instance, port) == nullptr) { - Pin *pin = network_->makePin(top_instance, port, nullptr); - network_->makeTerm(pin, net); + if (library_) { + Cell *top_cell = network_->findCell(library_, top_cell_name); + VerilogModule *module = this->module(top_cell); + if (module) { + // Seed the recursion for expansion with the top level instance. + Instance *top_instance = network_->makeInstance(top_cell, "", nullptr); + VerilogBindingTbl bindings(zero_net_name_, one_net_name_); + VerilogNetSeq::Iterator port_iter(module->ports()); + while (port_iter.hasNext()) { + VerilogNet *mod_port = port_iter.next(); + VerilogNetNameIterator *net_name_iter = mod_port->nameIterator(module, + this); + while (net_name_iter->hasNext()) { + const char *net_name = net_name_iter->next(); + Port *port = network_->findPort(top_cell, net_name); + Net *net = bindings.ensureNetBinding(net_name, top_instance, network_); + // Guard against repeated port name. + if (network_->findPin(top_instance, port) == nullptr) { + Pin *pin = network_->makePin(top_instance, port, nullptr); + network_->makeTerm(pin, net); + } } + delete net_name_iter; } - delete net_name_iter; + makeModuleInstBody(module, top_instance, &bindings, make_black_boxes); + bool errors = reportLinkErrors(report); + deleteModules(); + if (errors) { + network_->deleteInstance(top_instance); + return nullptr; + } + else + return top_instance; } - makeModuleInstBody(module, top_instance, &bindings, make_black_boxes); - bool errors = reportLinkErrors(report); - deleteModules(); - if (errors) { - network_->deleteInstance(top_instance); + else { + report->error("%s is not a verilog module.\n", top_cell_name); return nullptr; } - else - return top_instance; } else { report->error("%s is not a verilog module.\n", top_cell_name); @@ -1848,7 +1854,7 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst, parent_module, parent_bindings, is_leaf); } if (!is_leaf) { - VerilogModule *module = verilog_reader->module(cell); + VerilogModule *module = this->module(cell); makeModuleInstBody(module, inst, &bindings, make_black_boxes); } } diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc index 88d341d5..32ea7f22 100644 --- a/verilog/VerilogWriter.cc +++ b/verilog/VerilogWriter.cc @@ -66,14 +66,16 @@ writeVerilog(const char *filename, bool sort, Network *network) { - FILE *stream = fopen(filename, "w"); - if (stream) { - VerilogWriter writer(filename, sort, stream, network); - writer.writeModule(network->topInstance()); - fclose(stream); + if (network->topInstance()) { + FILE *stream = fopen(filename, "w"); + if (stream) { + VerilogWriter writer(filename, sort, stream, network); + writer.writeModule(network->topInstance()); + fclose(stream); + } + else + throw FileNotWritable(filename); } - else - throw FileNotWritable(filename); } VerilogWriter::VerilogWriter(const char *filename, @@ -117,8 +119,8 @@ VerilogWriter::writePorts(Cell *cell) Port *port = port_iter->next(); if (!first) fprintf(stream_, ",\n "); - fprintf(stream_, "%s", - network_->name(port)); + fprintf(stream_, "%s", portVerilogName(network_->name(port), + network_->pathEscape())); first = false; } delete port_iter; @@ -132,23 +134,23 @@ VerilogWriter::writePortDcls(Cell *cell) while (port_iter->hasNext()) { Port *port = port_iter->next(); PortDirection *dir = network_->direction(port); - if (dir) { - fprintf(stream_, " %s", - verilogPortDir(dir)); + const char *port_name = portVerilogName(network_->name(port), + network_->pathEscape()); + const char *vtype = verilogPortDir(dir); + if (vtype) { + fprintf(stream_, " %s", vtype); if (network_->isBus(port)) fprintf(stream_, " [%d:%d]", network_->fromIndex(port), network_->toIndex(port)); - fprintf(stream_, " %s;\n", - network_->name(port)); + fprintf(stream_, " %s;\n", port_name); if (dir->isTristate()) { fprintf(stream_, " tri"); if (network_->isBus(port)) - fprintf(stream_, " [%d:%d]", - network_->fromIndex(port), - network_->toIndex(port)); - fprintf(stream_, " %s;\n", - network_->name(port)); + fprintf(stream_, " [%d:%d]", + network_->fromIndex(port), + network_->toIndex(port)); + fprintf(stream_, " %s;\n", port_name); } } } @@ -226,7 +228,8 @@ VerilogWriter::writeInstPin(Instance *inst, const char *net_vname = netVerilogName(net_name, network_->pathEscape()); if (!first_port) fprintf(stream_, ",\n "); - const char *port_name = network_->name(port); + const char *port_name = portVerilogName(network_->name(port), + network_->pathEscape()); fprintf(stream_, ".%s(%s)", port_name, net_vname);