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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 382 311 Updated Feb 27, 2025

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

Python 25 3 Updated Aug 4, 2023

AISystem 主要是指AI系统,包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

Jupyter Notebook 12,617 1,818 Updated Jan 2, 2025

📚 C/C++ 技术面试基础知识总结,包括语言、程序库、数据结构、算法、系统、网络、链接装载库等知识及面试经验、招聘、内推等信息。This repository is a summary of the basic knowledge of recruiting job seekers and beginners in the direction of C/C++ technology, in…

C++ 35,527 8,025 Updated Mar 19, 2024

ABC: System for Sequential Logic Synthesis and Formal Verification

C 948 608 Updated Feb 23, 2025

egg is a flexible, high-performance e-graph library

Rust 1,434 147 Updated Dec 31, 2024

A Design Rule Checker with GPU Acceleration

C++ 48 9 Updated Sep 15, 2023

A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.

Python 160 17 Updated Feb 9, 2025

GPU-based logic synthesis tool

C++ 80 7 Updated Jul 16, 2024
Verilog 1 Updated Jan 19, 2025

Inference code for Llama models

Python 57,739 9,713 Updated Jan 26, 2025

A small utility to modify the dynamic linker and RPATH of ELF executables

C 3,730 494 Updated Feb 16, 2025
Jupyter Notebook 10 2 Updated Jun 30, 2024

Steiner Shallow-Light Tree for VLSI Routing

C++ 50 9 Updated Jul 11, 2024
C++ 5 Updated Jun 12, 2024

[CVPR 2021] Rethinking Semantic Segmentation from a Sequence-to-Sequence Perspective with Transformers

Python 1,064 149 Updated Sep 2, 2024

Latex code for making neural networks diagrams

TeX 22,805 2,924 Updated Aug 21, 2023

⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

Vue 6,982 477 Updated Feb 27, 2025

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,799 607 Updated Feb 27, 2025

Implementation of Our ISPD'19 Paper: Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing

C++ 8 2 Updated Jan 17, 2024

Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)

Python 16 2 Updated Jun 3, 2023

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Verilog 123 21 Updated Oct 10, 2024
Python 9 1 Updated Aug 26, 2023

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

C++ 99 20 Updated Mar 9, 2024
C++ 348 37 Updated Feb 19, 2025

DATC RDF

Verilog 49 12 Updated Jul 31, 2020

Introductory course into static timing analysis (STA).

Verilog 84 20 Updated Nov 3, 2024
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