From 4fa6be38ab7f34c3eb1521468b4046daad0b0ea8 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sat, 30 May 2020 17:09:34 +0200
Subject: [PATCH] More BmbGenerator peripherals

---
 .../main/scala/spinal/lib/bus/bmb/BmbCc.scala | 18 ++++++++++
 .../lib/com/spi/xdr/BmbSpiXdrMasterCtrl.scala | 33 +++++++++++++++++++
 lib/src/main/scala/spinal/lib/io/Gpio.scala   | 19 ++++++++++-
 3 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 lib/src/main/scala/spinal/lib/bus/bmb/BmbCc.scala
 create mode 100644 lib/src/main/scala/spinal/lib/com/spi/xdr/BmbSpiXdrMasterCtrl.scala

diff --git a/lib/src/main/scala/spinal/lib/bus/bmb/BmbCc.scala b/lib/src/main/scala/spinal/lib/bus/bmb/BmbCc.scala
new file mode 100644
index 0000000000..cebaf6f495
--- /dev/null
+++ b/lib/src/main/scala/spinal/lib/bus/bmb/BmbCc.scala
@@ -0,0 +1,18 @@
+package spinal.lib.bus.bmb
+
+import spinal.core._
+import spinal.lib._
+
+case class BmbCcFifo(p: BmbParameter,
+                     cmdDepth : Int,
+                     rspDepth : Int,
+                     inputCd: ClockDomain,
+                     outputCd: ClockDomain) extends Component{
+  val io = new Bundle {
+    val input = slave(Bmb(p))
+    val output = master(Bmb(p))
+  }
+
+  io.output.cmd << io.input.cmd.queue(cmdDepth, inputCd, outputCd)
+  io.input.rsp << io.output.rsp.queue(rspDepth, outputCd, inputCd)
+}
diff --git a/lib/src/main/scala/spinal/lib/com/spi/xdr/BmbSpiXdrMasterCtrl.scala b/lib/src/main/scala/spinal/lib/com/spi/xdr/BmbSpiXdrMasterCtrl.scala
new file mode 100644
index 0000000000..d7353bc933
--- /dev/null
+++ b/lib/src/main/scala/spinal/lib/com/spi/xdr/BmbSpiXdrMasterCtrl.scala
@@ -0,0 +1,33 @@
+package spinal.lib.com.spi.ddr
+
+import spinal.core._
+import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbParameter, BmbSlaveFactory}
+import spinal.lib.com.spi.ddr.SpiXdrMasterCtrl.{Cmd, Config, Rsp}
+import spinal.lib.{Flow, Stream, master, slave}
+
+
+
+object BmbSpiXdrMasterCtrl{
+  def getBmbCapabilities(accessSource : BmbAccessParameter) = BmbSlaveFactory.getBmbCapabilities(
+    accessSource,
+    addressWidth = addressWidth,
+    dataWidth = 32
+  )
+  def addressWidth = 12
+}
+
+
+case class BmbSpiXdrMasterCtrl(p : SpiXdrMasterCtrl.MemoryMappingParameters, ctrlParameter : BmbParameter) extends Component{
+  val io = new Bundle {
+    val ctrl = slave(Bmb(ctrlParameter))
+    val xip = ifGen(p.xip != null) (slave(SpiXdrMasterCtrl.XipBus(p.xip)))
+    val spi = master(SpiXdrMaster(p.ctrl.spi))
+    val interrupt = out Bool()
+  }
+
+  val ctrl = SpiXdrMasterCtrl(p.ctrl)
+  val mapping = SpiXdrMasterCtrl.driveFrom(ctrl, BmbSlaveFactory(io.ctrl))(p)
+  if(p.xip != null) io.xip <> mapping.xip.xipBus
+  io.spi <> ctrl.io.spi
+  io.interrupt <> mapping.interruptCtrl.interrupt
+}
diff --git a/lib/src/main/scala/spinal/lib/io/Gpio.scala b/lib/src/main/scala/spinal/lib/io/Gpio.scala
index c3fc72b00a..10043d5817 100644
--- a/lib/src/main/scala/spinal/lib/io/Gpio.scala
+++ b/lib/src/main/scala/spinal/lib/io/Gpio.scala
@@ -3,6 +3,7 @@ package spinal.lib.io
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory}
+import spinal.lib.bus.bmb.{Bmb, BmbAccessParameter, BmbParameter, BmbSlaveFactory}
 import spinal.lib.bus.misc.BusSlaveFactory
 
 object Gpio {
@@ -64,6 +65,8 @@ object Gpio {
       }
     }
   }
+
+  def addressWidth = 8
 }
 
 
@@ -73,4 +76,18 @@ case class Apb3Gpio2(  parameter: Gpio.Parameter,
   parameter,
   Apb3(busConfig),
   Apb3SlaveFactory(_)
-) { val dummy = 0 }
\ No newline at end of file
+)
+object BmbGpio2{
+  def getBmbCapabilities(accessSource : BmbAccessParameter) = BmbSlaveFactory.getBmbCapabilities(
+    accessSource,
+    addressWidth = Gpio.addressWidth,
+    dataWidth = 32
+  )
+}
+case class BmbGpio2(   parameter: Gpio.Parameter,
+                       busConfig: BmbParameter
+                    ) extends Gpio.Ctrl[Bmb] (
+  parameter,
+  Bmb(busConfig),
+  BmbSlaveFactory(_)
+)
\ No newline at end of file