Commits

Commits on Aug 6, 2023

Enhancements to balancing, LUT mapping, and rewriting (lsils#616 )
aletempiac
authoredAug 6, 2023

Commits on Jun 30, 2023

Realistic AQFP technology constraints (lsils#614 )
lee30sonia
authoredJun 30, 2023

Commits on Jun 28, 2023

Improved code quality and enabled the use of statistics in both new MIG inverter algorithms (lsils#613 )
marcelwa
authoredJun 28, 2023

Commits on Jun 27, 2023

Fixed compilation issues on MSVC compilers (lsils#612 )
marcelwa
authoredJun 27, 2023

Commits on Jun 6, 2023

Inverter optimization and propagation (lsils#610 )
BugraEryilmaz
authoredJun 6, 2023

Commits on Jun 2, 2023

Fix hashing and rewriting (lsils#609 )
aletempiac
authoredJun 2, 2023

Commits on Jun 1, 2023

Update README.md (lsils#608 )
aletempiac
authoredJun 1, 2023

Commits on May 31, 2023

Refactoring extensions and fixes (lsils#607 )
aletempiac
authoredMay 31, 2023
Adding GENLIB writer (lsils#606 )
aletempiac
authoredMay 31, 2023
In-place rewriting (lsils#605 )
aletempiac
authoredMay 31, 2023

Commits on Apr 27, 2023

Fix issues with write_blif on corner cases (lsils#603 )

authoredApr 27, 2023

Commits on Mar 28, 2023

Sequential cuts and mapping (lsils#599 )
aletempiac
authoredMar 28, 2023

Commits on Mar 23, 2023

LUT mapper updates (lsils#597 )
aletempiac
authoredMar 23, 2023

Commits on Mar 1, 2023

AQFP optimization methods (lsils#594 )
aletempiac
authoredMar 1, 2023

Commits on Jan 27, 2023

LUT mapper fixing issue lsils#592 (lsils#593 )

aletempiac
and
lee30sonia
authoredJan 27, 2023

Commits on Jan 18, 2023

Speed up CEC a little (lsils#590 )
lee30sonia
authoredJan 18, 2023
Added and fixed documentation on rank_view (lsils#591 )
marcelwa
authoredJan 18, 2023

Commits on Jan 11, 2023

Fix substitute_node; substitute without re-strashing (lsils#586 )
lee30sonia
authoredJan 11, 2023
crossed_klut_network and rank_view (lsils#589 )

lee30sonia
and
marcelwa
authoredJan 11, 2023

Commits on Jan 5, 2023

Support for external don't cares (lsils#585 )
lee30sonia
authoredJan 5, 2023

Commits on Dec 21, 2022

Fix truth table resizing on support minimization (lsils#584 )
aletempiac
authoredDec 21, 2022

Commits on Dec 13, 2022

Sequential circuit (lsils#573 )

authoredDec 13, 2022

Commits on Nov 29, 2022

LUT maper updates (lsils#582 )
aletempiac
authoredNov 29, 2022

Commits on Nov 28, 2022

Updates in resynthesis engines + various supports for MuxIG (lsils#575 )
lee30sonia
authoredNov 28, 2022
Typo (lsils#578 )

lrkkr
and
lee30sonia
authoredNov 28, 2022
LUT mapper (lsils#581 )
aletempiac
authoredNov 28, 2022
Algebraic methods for AIGs and XAGs (lsils#580 )
aletempiac
authoredNov 28, 2022

Commits on Nov 24, 2022

SOP factoring (lsils#579 )
aletempiac
authoredNov 24, 2022

Commits on Nov 22, 2022

[fix] typo (lsils#577 )
lrkkr
authoredNov 22, 2022

Commits on Nov 14, 2022

[fix] typo (lsils#576 )
lrkkr
authoredNov 14, 2022

Commits on Nov 10, 2022

Fix an issue in node substitution in XAG and XMG (lsils#574 )
lee30sonia
authoredNov 10, 2022

Commits on Sep 26, 2022

Mux inverter graph (lsils#569 )
mdsudara
authoredSep 26, 2022

Commits on Aug 8, 2022

Various fixes (lsils#567 )
lee30sonia
authoredAug 8, 2022

Commits on Aug 5, 2022

Update .readthedocs.yml
lee30sonia
authoredAug 5, 2022
Formating (lsils#566 )
lee30sonia
authoredAug 5, 2022