OpenCL Kernel Examples

This section contains OpenCL Kernel Examples.

Examples Table :

Example	Description	Key Concepts/Keywords
cl_array_partition	This example shows how to use array partitioning to improve performance of a kernel	Key Concepts Kernel Optimization Array Partition Keywords xcl_array_partition complete
cl_burst_rw	This is simple example of using AXI4-master interface for burst read and write	Key Concepts burst access Keywords compiler.interfaceRdBurstLen compiler.interfaceWrBurstLen
cl_dataflow_func	This is simple example of vector addition to demonstrate Dataflow functionality in OpenCL Kernel. OpenCL Dataflow allows user to run multiple functions together to achieve higher throughput.	Key Concepts Function/Task Level Parallelism Keywords xcl_dataflow xclDataflowFifoDepth
cl_dataflow_subfunc	This is simple example of vector addition to demonstrate how OpenCL Dataflow allows user to run multiple sub functions together to achieve higher throughput.	Key Concepts SubFunction Level Parallelism Keywords xcl_dataflow xclDataflowFifoDepth
cl_gmem_2banks	This example of 2ddr to demonstrate on how to use 2ddr XSA. How to create buffers in each DDR.	Key Concepts Multiple Banks Keywords sp connectivity
cl_helloworld	This example is a simple OpenCL application. It will highlight the basic flow of an OpenCL application.	Key Concepts OpenCL Host APIs
cl_lmem_2rw	This is simple example of vector addition to demonstrate how to utilized both ports of Local Memory.	Key Concepts Kernel Optimization 2port BRAM Utilization two read/write Local Memory Keywords opencl_unroll_hint
cl_loop_reorder	This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.	Key Concepts Kernel Optimization Loop reorder to improve II Keywords xcl_pipeline_loop xcl_array_partition
cl_partition_cyclicblock	This example shows how to use array block and cyclic partitioning to improve performance of a kernel	Key Concepts Kernel Optimization Array Partitioning Block Partition Cyclic Partition Keywords xcl_array_partition cyclic block
cl_shift_register	This example demonstrates how to shift values in registers in each clock cycle	Key Concepts Kernel Optimization Shift Register FIR Keywords xcl_array_partition getProfilingInfo
cl_systolic_array	This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note: Systolic array based algorithm design is well suited for FPGA.
cl_wide_mem_rw	This is simple example of vector addition to demonstrate Wide Memory Access using uint16 data type. Based on input argument type, V++ compiler will figure our the memory datawidth between Global Memory and Kernel. For this example, uint16 datatype is used, so Memory datawidth will be 16 x (integer bit size) = 16 x 32 = 512 bit.	Key Concepts Kernel to DDR wide memory access burst read and write Keywords uint16 xcl_pipeline_loop