A C-like to Verilog compiler
./veriexp input.ver > output.v
int a;
a = b + c * 2;
if (a < b) {
} else if (a > b) {
} else {
}
while (a) { ... }
func_name( args ) -> return_type
a = (f(addr=b, value=c) -> int) * d;
async fdone, fres = f(addr=b, value=c) -> d; await fdone;