Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."

Caused a hang and eventually an assertion failure in LTO builds
of 7zip-benchmark on aarch64 iOS targets.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330063 91177308-0d34-0410-b5e6-96231b3b80d8

Author: pcc

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -743,16 +743,14 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
     if (!GAN)
       return true;
 
-    if (GAN->getOffset() % Size == 0) {
-      const GlobalValue *GV = GAN->getGlobal();
-      unsigned Alignment = GV->getAlignment();
-      Type *Ty = GV->getValueType();
-      if (Alignment == 0 && Ty->isSized())
-        Alignment = DL.getABITypeAlignment(Ty);
-
-      if (Alignment >= Size)
-        return true;
-    }
+    const GlobalValue *GV = GAN->getGlobal();
+    unsigned Alignment = GV->getAlignment();
+    Type *Ty = GV->getValueType();
+    if (Alignment == 0 && Ty->isSized())
+      Alignment = DL.getABITypeAlignment(Ty);
+
+    if (Alignment >= Size)
+      return true;
   }
 
   if (CurDAG->isBaseWithConstantOffset(N)) {

lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -577,8 +577,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
   setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
 
-  setTargetDAGCombine(ISD::GlobalAddress);
-
   MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
   MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
   MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
@@ -3679,8 +3677,7 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
                                              SelectionDAG &DAG,
                                              unsigned Flag) const {
-  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty,
-                                    N->getOffset(), Flag);
+  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
 }
 
 SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
@@ -3755,9 +3752,8 @@ SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
   unsigned char OpFlags =
       Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
 
-  if (OpFlags != AArch64II::MO_NO_FLAG)
-    assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
-           "unexpected offset in global node");
+  assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
+         "unexpected offset in global node");
 
   // This also catches the large code model case for Darwin.
   if ((OpFlags & AArch64II::MO_GOT) != 0) {
@@ -4995,8 +4991,10 @@ SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
 
 bool AArch64TargetLowering::isOffsetFoldingLegal(
     const GlobalAddressSDNode *GA) const {
-  // Offsets are folded in the DAG combine rather than here so that we can
-  // intelligently choose an offset based on the uses.
+  DEBUG(dbgs() << "Skipping offset folding global address: ");
+  DEBUG(GA->dump());
+  DEBUG(dbgs() << "AArch64 doesn't support folding offsets into global "
+        "addresses\n");
   return false;
 }
 
@@ -10619,53 +10617,6 @@ static SDValue performNVCASTCombine(SDNode *N) {
   return SDValue();
 }
 
-// If all users of the globaladdr are of the form (globaladdr + constant), find
-// the smallest constant, fold it into the globaladdr's offset and rewrite the
-// globaladdr as (globaladdr + constant) - constant.
-static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
-                                           const AArch64Subtarget *Subtarget,
-                                           const TargetMachine &TM) {
-  auto *GN = dyn_cast<GlobalAddressSDNode>(N);
-  if (!GN || Subtarget->ClassifyGlobalReference(GN->getGlobal(), TM) !=
-                 AArch64II::MO_NO_FLAG)
-    return SDValue();
-
-  uint64_t MinOffset = -1ull;
-  for (SDNode *N : GN->uses()) {
-    if (N->getOpcode() != ISD::ADD)
-      return SDValue();
-    auto *C = dyn_cast<ConstantSDNode>(N->getOperand(0));
-    if (!C)
-      C = dyn_cast<ConstantSDNode>(N->getOperand(1));
-    if (!C)
-      return SDValue();
-    MinOffset = std::min(MinOffset, C->getZExtValue());
-  }
-  uint64_t Offset = MinOffset + GN->getOffset();
-
-  // Check whether folding this offset is legal. It must not go out of bounds of
-  // the referenced object to avoid violating the code model, and must be
-  // smaller than 2^21 because this is the largest offset expressible in all
-  // object formats.
-  //
-  // This check also prevents us from folding negative offsets, which will end
-  // up being treated in the same way as large positive ones. They could also
-  // cause code model violations, and aren't really common enough to matter.
-  if (Offset >= (1 << 21))
-    return SDValue();
-
-  const GlobalValue *GV = GN->getGlobal();
-  Type *T = GV->getValueType();
-  if (!T->isSized() ||
-      Offset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
-    return SDValue();
-
-  SDLoc DL(GN);
-  SDValue Result = DAG.getGlobalAddress(GV, DL, MVT::i64, Offset);
-  return DAG.getNode(ISD::SUB, DL, MVT::i64, Result,
-                     DAG.getConstant(MinOffset, DL, MVT::i64));
-}
-
 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
                                                  DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
@@ -10753,8 +10704,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
     default:
       break;
     }
-  case ISD::GlobalAddress:
-    return performGlobalAddressCombine(N, DAG, Subtarget, getTargetMachine());
   }
   return SDValue();
 }

test/CodeGen/AArch64/arm64-addrmode.ll

@@ -5,42 +5,43 @@
 
 ; base + offset (imm9)
 ; CHECK: @t1
-; CHECK: ldr xzr, [x0, #8]
+; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
 ; CHECK: ret
-define void @t1(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 1
+define void @t1() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + offset (> imm9)
 ; CHECK: @t2
-; CHECK: sub [[ADDREG:x[0-9]+]], x0, #264
+; CHECK: sub [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #264
 ; CHECK: ldr xzr, [
+; CHECK: [[ADDREG]]]
 ; CHECK: ret
-define void @t2(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 -33
+define void @t2() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
 ; CHECK: @t3
-; CHECK: ldr xzr, [x0, #32760]
+; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
 ; CHECK: ret
-define void @t3(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4095
+define void @t3() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
 
 ; base + unsigned offset (> imm12 * size of type in bytes)
 ; CHECK: @t4
 ; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
-; CHECK: ldr xzr, [x0, x[[NUM]]]
+; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
-define void @t4(i64* %object) {
-  %incdec.ptr = getelementptr inbounds i64, i64* %object, i64 4096
+define void @t4() {
+  %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void
 }
@@ -57,12 +58,12 @@ define void @t5(i64 %a) {
 
 ; base + reg + imm
 ; CHECK: @t6
-; CHECK: add [[ADDREG:x[0-9]+]], x1, x0, lsl #3
+; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3
 ; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
 ; CHECK: ret
-define void @t6(i64 %a, i64* %object) {
-  %tmp1 = getelementptr inbounds i64, i64* %object, i64 %a
+define void @t6(i64 %a) {
+  %tmp1 = getelementptr inbounds i64, i64* @object, i64 %a
   %incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096
   %tmp = load volatile i64, i64* %incdec.ptr, align 8
   ret void