forked from flashrom/flashrom
-
Notifications
You must be signed in to change notification settings - Fork 0
/
board_enable.c
2295 lines (2002 loc) · 73.2 KB
/
board_enable.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* This file is part of the flashrom project.
*
* Copyright (C) 2005-2007 coresystems GmbH <[email protected]>
* Copyright (C) 2006 Uwe Hermann <[email protected]>
* Copyright (C) 2007-2009 Luc Verhaegen <[email protected]>
* Copyright (C) 2007 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Contains the board specific flash enables.
*/
#include <string.h>
#include "flash.h"
#include "programmer.h"
#if defined(__i386__) || defined(__x86_64__)
/*
* Helper functions for many Winbond Super I/Os of the W836xx range.
*/
/* Enter extended functions */
void w836xx_ext_enter(uint16_t port)
{
OUTB(0x87, port);
OUTB(0x87, port);
}
/* Leave extended functions */
void w836xx_ext_leave(uint16_t port)
{
OUTB(0xAA, port);
}
/* Generic Super I/O helper functions */
uint8_t sio_read(uint16_t port, uint8_t reg)
{
OUTB(reg, port);
return INB(port + 1);
}
void sio_write(uint16_t port, uint8_t reg, uint8_t data)
{
OUTB(reg, port);
OUTB(data, port + 1);
}
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
{
uint8_t tmp;
OUTB(reg, port);
tmp = INB(port + 1) & ~mask;
OUTB(tmp | (data & mask), port + 1);
}
/* Not used yet. */
#if 0
static int enable_flash_decode_superio(void)
{
int ret;
uint8_t tmp;
switch (superio.vendor) {
case SUPERIO_VENDOR_NONE:
ret = -1;
break;
case SUPERIO_VENDOR_ITE:
enter_conf_mode_ite(superio.port);
/* Enable flash mapping. Works for most old ITE style Super I/O. */
tmp = sio_read(superio.port, 0x24);
tmp |= 0xfc;
sio_write(superio.port, 0x24, tmp);
exit_conf_mode_ite(superio.port);
ret = 0;
break;
default:
msg_pdbg("Unhandled Super I/O type!\n");
ret = -1;
break;
}
return ret;
}
#endif
/*
* SMSC FDC37B787: Raise GPIO50
*/
static int fdc37b787_gpio50_raise(uint16_t port)
{
uint8_t id, val;
OUTB(0x55, port); /* enter conf mode */
id = sio_read(port, 0x20);
if (id != 0x44) {
msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
OUTB(0xAA, port); /* leave conf mode */
return -1;
}
sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
val = sio_read(port, 0xC8); /* GP50 */
if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
{
msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
OUTB(0xAA, port);
return -1;
}
sio_mask(port, 0xF9, 0x01, 0x01);
OUTB(0xAA, port); /* Leave conf mode */
return 0;
}
/*
* Suited for:
* - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
*/
static int fdc37b787_gpio50_raise_3f0(void)
{
return fdc37b787_gpio50_raise(0x3f0);
}
struct winbond_mux {
uint8_t reg; /* 0 if the corresponding pin is not muxed */
uint8_t data; /* reg/data/mask may be directly ... */
uint8_t mask; /* ... passed to sio_mask */
};
struct winbond_port {
const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
uint8_t ldn; /* LDN this GPIO register is located in */
uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
the GPIO port */
uint8_t base; /* base register in that LDN for the port */
};
struct winbond_chip {
uint8_t device_id; /* reg 0x20 of the expected w83626x */
uint8_t gpio_port_count;
const struct winbond_port *port;
};
#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
enum winbond_id {
WINBOND_W83627HF_ID = 0x52,
WINBOND_W83627EHF_ID = 0x88,
WINBOND_W83627THF_ID = 0x82,
};
static const struct winbond_mux w83627hf_port2_mux[8] = {
{0x2A, 0x01, 0x01}, /* or MIDI */
{0x2B, 0x80, 0x80}, /* or SPI */
{0x2B, 0x40, 0x40}, /* or SPI */
{0x2B, 0x20, 0x20}, /* or power LED */
{0x2B, 0x10, 0x10}, /* or watchdog */
{0x2B, 0x08, 0x08}, /* or infra red */
{0x2B, 0x04, 0x04}, /* or infra red */
{0x2B, 0x03, 0x03} /* or IRQ1 input */
};
static const struct winbond_port w83627hf[3] = {
UNIMPLEMENTED_PORT,
{w83627hf_port2_mux, 0x08, 0, 0xF0},
UNIMPLEMENTED_PORT,
};
static const struct winbond_mux w83627ehf_port2_mux[8] = {
{0x29, 0x06, 0x02}, /* or MIDI */
{0x29, 0x06, 0x02},
{0x24, 0x02, 0x00}, /* or SPI ROM interface */
{0x24, 0x02, 0x00},
{0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
{0x2A, 0x01, 0x01},
{0x2A, 0x01, 0x01},
{0x2A, 0x01, 0x01},
};
static const struct winbond_port w83627ehf[6] = {
UNIMPLEMENTED_PORT,
{w83627ehf_port2_mux, 0x09, 0, 0xE3},
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
};
static const struct winbond_mux w83627thf_port4_mux[8] = {
{0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
{0x2D, 0x02, 0x02}, /* or resume reset */
{0x2D, 0x04, 0x04}, /* or S3 input */
{0x2D, 0x08, 0x08}, /* or PSON# */
{0x2D, 0x10, 0x10}, /* or PWROK */
{0x2D, 0x20, 0x20}, /* or suspend LED */
{0x2D, 0x40, 0x40}, /* or panel switch input */
{0x2D, 0x80, 0x80}, /* or panel switch output */
};
static const struct winbond_port w83627thf[5] = {
UNIMPLEMENTED_PORT, /* GPIO1 */
UNIMPLEMENTED_PORT, /* GPIO2 */
UNIMPLEMENTED_PORT, /* GPIO3 */
{w83627thf_port4_mux, 0x09, 1, 0xF4},
UNIMPLEMENTED_PORT, /* GPIO5 */
};
static const struct winbond_chip winbond_chips[] = {
{WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
{WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
{WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
};
/*
* Detects which Winbond Super I/O is responding at the given base address,
* but takes no effort to make sure the chip is really a Winbond Super I/O.
*/
static const struct winbond_chip *winbond_superio_detect(uint16_t base)
{
uint8_t chipid;
const struct winbond_chip *chip = NULL;
int i;
w836xx_ext_enter(base);
chipid = sio_read(base, 0x20);
for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {
if (winbond_chips[i].device_id == chipid) {
chip = &winbond_chips[i];
break;
}
}
w836xx_ext_leave(base);
return chip;
}
/*
* The chipid parameter goes away as soon as we have Super I/O matching in the
* board enable table. The call to winbond_superio_detect() goes away as
* soon as we have generic Super I/O detection code.
*/
static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
int pin, int raise)
{
const struct winbond_chip *chip = NULL;
const struct winbond_port *gpio;
int port = pin / 10;
int bit = pin % 10;
chip = winbond_superio_detect(base);
if (!chip) {
msg_perr("\nERROR: No supported Winbond Super I/O found\n");
return -1;
}
if (chip->device_id != chipid) {
msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
"expected %x\n", chip->device_id, chipid);
return -1;
}
if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
pin);
return -1;
}
gpio = &chip->port[port - 1];
if (gpio->ldn == 0) {
msg_perr("\nERROR: GPIO%d is not supported yet on this"
" winbond chip\n", port);
return -1;
}
w836xx_ext_enter(base);
/* Select logical device. */
sio_write(base, 0x07, gpio->ldn);
/* Activate logical device. */
sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
/* Select GPIO function of that pin. */
if (gpio->mux && gpio->mux[bit].reg)
sio_mask(base, gpio->mux[bit].reg,
gpio->mux[bit].data, gpio->mux[bit].mask);
sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
w836xx_ext_leave(base);
return 0;
}
/*
* Winbond W83627HF: Raise GPIO24.
*
* Suited for:
* - Agami Aruma
* - IWILL DK8-HTX
*/
static int w83627hf_gpio24_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
}
/*
* Winbond W83627HF: Raise GPIO25.
*
* Suited for:
* - MSI MS-6577
*/
static int w83627hf_gpio25_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
}
/*
* Winbond W83627EHF: Raise GPIO22.
*
* Suited for:
* - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
*/
static int w83627ehf_gpio22_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
}
/*
* Winbond W83627THF: Raise GPIO 44.
*
* Suited for:
* - MSI K8T Neo2-F
*/
static int w83627thf_gpio44_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
}
/*
* Winbond W83627THF: Raise GPIO 44.
*
* Suited for:
* - MSI K8N Neo3
*/
static int w83627thf_gpio44_raise_4e(void)
{
return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
}
/*
* Enable MEMW# and set ROM size to max.
* Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
*/
static void w836xx_memw_enable(uint16_t port)
{
w836xx_ext_enter(port);
if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
/* Enable MEMW# and set ROM size select to max. (4M). */
sio_mask(port, 0x24, 0x28, 0x28);
}
w836xx_ext_leave(port);
}
/*
* Suited for:
* - EPoX EP-8K5A2: VIA KT333 + VT8235
* - Albatron PM266A Pro: VIA P4M266A + VT8235
* - Shuttle AK31 (all versions): VIA KT266 + VT8233
* - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
* - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
* - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
* - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
* - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
* - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
* - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
*/
static int w836xx_memw_enable_2e(void)
{
w836xx_memw_enable(0x2E);
return 0;
}
/*
* Suited for:
* - Termtek TK-3370 (rev. 2.5b)
*/
static int w836xx_memw_enable_4e(void)
{
w836xx_memw_enable(0x4E);
return 0;
}
/*
* Suited for all boards with ITE IT8705F.
* The SIS950 Super I/O probably requires a similar flash write enable.
*/
int it8705f_write_enable(uint8_t port)
{
uint8_t tmp;
int ret = 0;
enter_conf_mode_ite(port);
tmp = sio_read(port, 0x24);
/* Check if at least one flash segment is enabled. */
if (tmp & 0xf0) {
/* The IT8705F will respond to LPC cycles and translate them. */
buses_supported = BUS_PARALLEL;
/* Flash ROM I/F Writes Enable */
tmp |= 0x04;
msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
if (tmp & 0x02) {
/* The data sheet contradicts itself about max size. */
max_rom_decode.parallel = 1024 * 1024;
msg_pinfo("IT8705F with very unusual settings. Please "
"send the output of \"flashrom -V\" to \n"
"[email protected] with "
"IT8705: your board name: flashrom -V\n"
"as the subject to help us finish "
"support for your Super I/O. Thanks.\n");
ret = 1;
} else if (tmp & 0x08) {
max_rom_decode.parallel = 512 * 1024;
} else {
max_rom_decode.parallel = 256 * 1024;
}
/* Safety checks. The data sheet is unclear here: Segments 1+3
* overlap, no segment seems to cover top - 1MB to top - 512kB.
* We assume that certain combinations make no sense.
*/
if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
(!(tmp & 0x10)) || /* 128 kB dis */
(!(tmp & 0x40))) { /* 256/512 kB dis */
msg_perr("Inconsistent IT8705F decode size!\n");
ret = 1;
}
if (sio_read(port, 0x25) != 0) {
msg_perr("IT8705F flash data pins disabled!\n");
ret = 1;
}
if (sio_read(port, 0x26) != 0) {
msg_perr("IT8705F flash address pins 0-7 disabled!\n");
ret = 1;
}
if (sio_read(port, 0x27) != 0) {
msg_perr("IT8705F flash address pins 8-15 disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x10) != 0) {
msg_perr("IT8705F flash write enable pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x08) != 0) {
msg_perr("IT8705F flash chip select pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x04) != 0) {
msg_perr("IT8705F flash read strobe pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x03) != 0) {
msg_perr("IT8705F flash address pins 16-17 disabled!\n");
/* Not really an error if you use flash chips smaller
* than 256 kByte, but such a configuration is unlikely.
*/
ret = 1;
}
msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
max_rom_decode.parallel);
if (ret) {
msg_pinfo("Not enabling IT8705F flash write.\n");
} else {
sio_write(port, 0x24, tmp);
}
} else {
msg_pdbg("No IT8705F flash segment enabled.\n");
ret = 0;
}
exit_conf_mode_ite(port);
return ret;
}
/*
* The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
* It uses the Winbond command sequence to enter extended configuration
* mode and the ITE sequence to exit.
*
* Registers seems similar to the ones on ITE IT8710F.
*/
static int it8707f_write_enable(uint8_t port)
{
uint8_t tmp;
w836xx_ext_enter(port);
/* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
tmp = sio_read(port, 0x23);
tmp |= (1 << 3);
sio_write(port, 0x23, tmp);
/* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
tmp = sio_read(port, 0x24);
tmp |= (1 << 2) | (1 << 3);
sio_write(port, 0x24, tmp);
/* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
tmp = sio_read(port, 0x23);
tmp &= ~(1 << 3);
sio_write(port, 0x23, tmp);
exit_conf_mode_ite(port);
return 0;
}
/*
* Suited for:
* - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
*/
static int it8707f_write_enable_2e(void)
{
return it8707f_write_enable(0x2e);
}
#define PC87360_ID 0xE1
#define PC87364_ID 0xE4
static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
{
static const int bankbase[] = {0, 4, 8, 10, 12};
int gpio_bank = gpio / 8;
int gpio_pin = gpio % 8;
uint16_t baseport;
uint8_t id, val;
if (gpio_bank > 4) {
msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
return -1;
}
id = sio_read(0x2E, 0x20);
if (id != chipid) {
msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
id, chipid);
return -1;
}
sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
msg_perr("PC87360: invalid GPIO base address %04x\n",
baseport);
return -1;
}
sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
val = INB(baseport + bankbase[gpio_bank]);
if (raise)
val |= 1 << gpio_pin;
else
val &= ~(1 << gpio_pin);
OUTB(val, baseport + bankbase[gpio_bank]);
return 0;
}
/*
* VIA VT823x: Set one of the GPIO pins.
*/
static int via_vt823x_gpio_set(uint8_t gpio, int raise)
{
struct pci_dev *dev;
uint16_t base;
uint8_t val, bit, offset;
dev = pci_dev_find_vendorclass(0x1106, 0x0601);
switch (dev->device_id) {
case 0x3177: /* VT8235 */
case 0x3227: /* VT8237R */
case 0x3337: /* VT8237A */
break;
default:
msg_perr("\nERROR: VT823x ISA bridge not found.\n");
return -1;
}
if ((gpio >= 12) && (gpio <= 15)) {
/* GPIO12-15 -> output */
val = pci_read_byte(dev, 0xE4);
val |= 0x10;
pci_write_byte(dev, 0xE4, val);
} else if (gpio == 9) {
/* GPIO9 -> Output */
val = pci_read_byte(dev, 0xE4);
val |= 0x20;
pci_write_byte(dev, 0xE4, val);
} else if (gpio == 5) {
val = pci_read_byte(dev, 0xE4);
val |= 0x01;
pci_write_byte(dev, 0xE4, val);
} else {
msg_perr("\nERROR: "
"VT823x GPIO%02d is not implemented.\n", gpio);
return -1;
}
/* We need the I/O Base Address for this board's flash enable. */
base = pci_read_word(dev, 0x88) & 0xff80;
offset = 0x4C + gpio / 8;
bit = 0x01 << (gpio % 8);
val = INB(base + offset);
if (raise)
val |= bit;
else
val &= ~bit;
OUTB(val, base + offset);
return 0;
}
/*
* Suited for:
* - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
*/
static int via_vt823x_gpio5_raise(void)
{
/* On M2V-MX: GPO5 is connected to WP# and TBL#. */
return via_vt823x_gpio_set(5, 1);
}
/*
* Suited for:
* - VIA EPIA EK & N & NL
*/
static int via_vt823x_gpio9_raise(void)
{
return via_vt823x_gpio_set(9, 1);
}
/*
* Suited for:
* - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
*
* We don't need to do this for EPIA M when using coreboot, GPIO15 is never
* lowered there.
*/
static int via_vt823x_gpio15_raise(void)
{
return via_vt823x_gpio_set(15, 1);
}
/*
* Winbond W83697HF Super I/O + VIA VT8235 southbridge
*
* Suited for:
* - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
* - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
*/
static int board_msi_kt4v(void)
{
int ret;
ret = via_vt823x_gpio_set(12, 1);
w836xx_memw_enable(0x2E);
return ret;
}
/*
* Suited for:
* - ASUS P5A
*
* This is rather nasty code, but there's no way to do this cleanly.
* We're basically talking to some unknown device on SMBus, my guess
* is that it is the Winbond W83781D that lives near the DIP BIOS.
*/
static int board_asus_p5a(void)
{
uint8_t tmp;
int i;
#define ASUSP5A_LOOP 5000
OUTB(0x00, 0xE807);
OUTB(0xEF, 0xE803);
OUTB(0xFF, 0xE800);
for (i = 0; i < ASUSP5A_LOOP; i++) {
OUTB(0xE1, 0xFF);
if (INB(0xE800) & 0x04)
break;
}
if (i == ASUSP5A_LOOP) {
msg_perr("Unable to contact device.\n");
return -1;
}
OUTB(0x20, 0xE801);
OUTB(0x20, 0xE1);
OUTB(0xFF, 0xE802);
for (i = 0; i < ASUSP5A_LOOP; i++) {
tmp = INB(0xE800);
if (tmp & 0x70)
break;
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
msg_perr("Failed to read device.\n");
return -1;
}
tmp = INB(0xE804);
tmp &= ~0x02;
OUTB(0x00, 0xE807);
OUTB(0xEE, 0xE803);
OUTB(tmp, 0xE804);
OUTB(0xFF, 0xE800);
OUTB(0xE1, 0xFF);
OUTB(0x20, 0xE801);
OUTB(0x20, 0xE1);
OUTB(0xFF, 0xE802);
for (i = 0; i < ASUSP5A_LOOP; i++) {
tmp = INB(0xE800);
if (tmp & 0x70)
break;
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
msg_perr("Failed to write to device.\n");
return -1;
}
return 0;
}
/*
* Set GPIO lines in the Broadcom HT-1000 southbridge.
*
* It's not a Super I/O but it uses the same index/data port method.
*/
static int board_hp_dl145_g3_enable(void)
{
/* GPIO 0 reg from PM regs */
/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
sio_mask(0xcd6, 0x44, 0x24, 0x24);
return 0;
}
/*
* Set GPIO lines in the Broadcom HT-1000 southbridge.
*
* It's not a Super I/O but it uses the same index/data port method.
*/
static int board_hp_dl165_g6_enable(void)
{
/* Variant of DL145, with slightly different pin placement. */
sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
return 0;
}
static int board_ibm_x3455(void)
{
/* Raise GPIO13. */
sio_mask(0xcd6, 0x45, 0x20, 0x20);
return 0;
}
/*
* Suited for:
* - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
*/
static int board_shuttle_fn25(void)
{
struct pci_dev *dev;
dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA bridge. */
if (!dev) {
msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
return -1;
}
/* One of those bits seems to be connected to TBL#, but -ENOINFO. */
pci_write_byte(dev, 0x92, 0);
return 0;
}
/*
* Suited for:
* - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
*/
static int board_ecs_geforce6100sm_m(void)
{
struct pci_dev *dev;
uint32_t tmp;
dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
if (!dev) {
msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
return -1;
}
tmp = pci_read_byte(dev, 0xE0);
tmp &= ~(1 << 3);
pci_write_byte(dev, 0xE0, tmp);
return 0;
}
/*
* Very similar to AMD 8111 IO Hub.
*/
static int nvidia_mcp_gpio_set(int gpio, int raise)
{
struct pci_dev *dev;
uint16_t base, devclass;
uint8_t tmp;
if ((gpio < 0) || (gpio >= 0x40)) {
msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
return -1;
}
/* Check for the ISA bridge first. */
dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
switch (dev->device_id) {
case 0x0030: /* CK804 */
case 0x0050: /* MCP04 */
case 0x0060: /* MCP2 */
case 0x00E0: /* CK8 */
break;
case 0x0260: /* MCP51 */
case 0x0261: /* MCP51 */
case 0x0364: /* MCP55 */
/* find SMBus controller on *this* southbridge */
/* The infamous Tyan S2915-E has two south bridges; they are
easily told apart from each other by the class of the
LPC bridge, but have the same SMBus bridge IDs */
if (dev->func != 0) {
msg_perr("MCP LPC bridge at unexpected function"
" number %d\n", dev->func);
return -1;
}
#if PCI_LIB_VERSION >= 0x020200
dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
#else
/* pciutils/libpci before version 2.2 is too old to support
* PCI domains. Such old machines usually don't have domains
* besides domain 0, so this is not a problem.
*/
dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
#endif
if (!dev) {
msg_perr("MCP SMBus controller could not be found\n");
return -1;
}
devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
if (devclass != 0x0C05) {
msg_perr("Unexpected device class %04x for SMBus"
" controller\n", devclass);
return -1;
}
break;
default:
msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
return -1;
}
base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
base += 0xC0;
tmp = INB(base + gpio);
tmp &= ~0x0F; /* null lower nibble */
tmp |= 0x04; /* gpio -> output. */
if (raise)
tmp |= 0x01;
OUTB(tmp, base + gpio);
return 0;
}
/*
* Suited for:
* - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
* - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
* - ASUS M2NBP-VM CSM: NVIDIA MCP51
*/
static int nvidia_mcp_gpio0_raise(void)
{
return nvidia_mcp_gpio_set(0x00, 1);
}
/*
* Suited for:
* - abit KN8 Ultra: NVIDIA CK804
*/
static int nvidia_mcp_gpio2_lower(void)
{
return nvidia_mcp_gpio_set(0x02, 0);
}
/*
* Suited for:
* - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
* - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
* - MSI K8NGM2-L: NVIDIA MCP51
*/
static int nvidia_mcp_gpio2_raise(void)
{
return nvidia_mcp_gpio_set(0x02, 1);
}
/*
* Suited for:
* - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
*/
static int nvidia_mcp_gpio4_raise(void)
{
return nvidia_mcp_gpio_set(0x04, 1);
}
/*
* Suited for:
* - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
*
* Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
* board. We can't tell the SMBus logical devices apart, but we
* can tell the LPC bridge functions apart.
* We need to choose the SMBus bridge next to the LPC bridge with
* ID 0x364 and the "LPC bridge" class.
* b) #TBL is hardwired on that board to a pull-down. It can be
* overridden by connecting the two solder points next to F2.
*/
static int nvidia_mcp_gpio5_raise(void)
{
return nvidia_mcp_gpio_set(0x05, 1);
}
/*
* Suited for:
* - abit NF7-S: NVIDIA CK804
*/
static int nvidia_mcp_gpio8_raise(void)
{
return nvidia_mcp_gpio_set(0x08, 1);
}
/*
* Suited for:
* - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
*/
static int nvidia_mcp_gpio0a_raise(void)
{
return nvidia_mcp_gpio_set(0x0a, 1);
}
/*
* Suited for:
* - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
*/