5.1_chisel_util_basic.ipynb

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    "<a name=\"top\"></a><img src=\"images/chisel_1024.png\" alt=\"Chisel logo\" style=\"width:480px;\" />"
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   "source": [
    "# Module 5.1: Get familiar with Chisel Utilities\n",
    "**Prev: [Introduction to Scala](1_intro_to_scala.ipynb)**<br>\n",
    "**Next: [Combinational Logic](2.2_comb_logic.ipynb)**\n",
    "\n",
    "## Motivation\n",
    "Set up a playground to get familar with various Chisel Unitility"
   ]
  },
  {
   "cell_type": "markdown",
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   "source": [
    "## Setup\n",
    "The following cell downloads the dependencies needed for Chisel. You will see it in all future notebooks. **Run this cell now**."
   ]
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   "cell_type": "code",
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   "source": [
    "val path = System.getProperty(\"user.dir\") + \"/source/load-ivy.sc\"\n",
    "interp.load.module(ammonite.ops.Path(java.nio.file.FileSystems.getDefault().getPath(path)))"
   ]
  },
  {
   "cell_type": "markdown",
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   "source": [
    "As mentioned in the last module, these statements are needed to import Chisel. **Run this cell now** before running any future code blocks."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": [
    "import chisel3._\n",
    "import chisel3.util._\n",
    "import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "---\n",
    "# Simple Example\n",
    "\n",
    "<span style=\"color:blue\">**Example: A Module**</span><br>\n",
    "Like Verilog, we can declare module definitions in Chisel. The following example is a Chisel `Module`, `Passthrough`, that has one 4-bit input, `in`, and one 4-bit output, `out`. The module combinationally connects `in` and `out`, so `in` drives `out`."
   ]
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   "source": [
    "// scala type\n",
    "// chisel type\n",
    "// hardware: Bool\n",
    "class SimpleModule(width: Int) extends Module {\n",
    "    val io = IO(new Bundle {\n",
    "        val in = Input(UInt(width.W))\n",
    "        val out = Output(UInt(1.W))\n",
    "})\n",
    "    io.out := io.in.orR\n",
    "\n",
    "}"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": [
    "// Viewing the Verilog for debugging\n",
    "println(getVerilog(new SimpleModule(10)))"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": [
    "// Viewing the firrtl for debugging\n",
    "println(getFirrtl(new SimpleModule(10)))"
   ]
  }
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