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9 stars written in Verilog
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RTL, Cmodel, and testbench for NVDLA

Verilog 1,795 575 Updated Mar 2, 2022

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,734 595 Updated Jan 29, 2025

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Verilog 637 105 Updated Nov 15, 2024

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Verilog 345 108 Updated Jan 14, 2022

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Verilog 264 65 Updated Jul 28, 2020

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

Verilog 156 56 Updated May 11, 2023

XCrypto: a cryptographic ISE for RISC-V

Verilog 92 10 Updated Jan 5, 2023

A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano

Verilog 13 4 Updated Apr 15, 2019

XCrypto: a cryptographic ISE for RISC-V

Verilog 5 1 Updated Jun 27, 2019