diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala
index 0e54dd3be33..37df20e191f 100644
--- a/src/main/scala/xiangshan/backend/CtrlBlock.scala
+++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala
@@ -305,10 +305,6 @@ class CtrlBlockImp(
   decode.io.commitVType := rob.io.toDecode.commitVType
   decode.io.walkVType := rob.io.toDecode.walkVType
 
-  // spec vtype, from vtypegen to vtpebuffer
-  rob.io.fromDecode.lastSpecVType := decode.io.lastSpecVType
-  rob.io.fromDecode.specVtype := decode.io.specVtype
-
   decode.io.redirect := s1_s3_redirect.valid || s2_s4_pendingRedirectValid
   decode.io.vtypeRedirect := s1_s3_redirect.valid
 
diff --git a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
index 3fe6c078ed5..41df821942a 100644
--- a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
+++ b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
@@ -66,8 +66,6 @@ class DecodeStage(implicit p: Parameters) extends XSModule
     }
     val vsetvlVType = Input(VType())
     val vstart = Input(Vl())
-    val lastSpecVType = (Valid(new VType))
-    val specVtype = Output(new VType)
   })
 
   // io alias
@@ -114,8 +112,6 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   vtypeGen.io.commitVType := io.commitVType
   vtypeGen.io.walkVType := io.walkVType
   vtypeGen.io.vsetvlVType := io.vsetvlVType
-  io.specVtype := vtypeGen.io.specVtype
-  io.lastSpecVType := vtypeGen.io.lastSpecVType
 
   //Comp 1
   decoderComp.io.redirect := io.redirect
diff --git a/src/main/scala/xiangshan/backend/decode/VTypeGen.scala b/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
index 954f4fc95e0..cabdd2c46c2 100644
--- a/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
+++ b/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
@@ -20,8 +20,6 @@ class VTypeGen(implicit p: Parameters) extends XSModule{
       val vtype = Flipped(Valid(new VType))
       val hasVsetvl = Input(Bool())
     }
-    val lastSpecVType = (Valid(new VType))
-    val specVtype = Output(new VType)
   })
   private val instValidVec = io.insts.map(_.valid)
   private val instFieldVec = io.insts.map(_.bits.asTypeOf(new XSInstBitFields))
@@ -43,15 +41,12 @@ class VTypeGen(implicit p: Parameters) extends XSModule{
 
   private val vtypeArch = RegInit(0.U.asTypeOf(new VType))
   private val vtypeSpec = RegInit(0.U.asTypeOf(new VType))
-  private val lastSpecVType = RegInit(0.U.asTypeOf(new ValidIO(VType())))
 
   private val vtypeArchNext = WireInit(vtypeArch)
   private val vtypeSpecNext = WireInit(vtypeSpec)
-  private val lastSpecVTypeNext = WireInit(lastSpecVType)
 
   vtypeArch := vtypeArchNext
   vtypeSpec := vtypeSpecNext
-  lastSpecVType := lastSpecVTypeNext
 
   private val instVType: InstVType = Mux(isVsetvli, firstVsetInstField.ZIMM_VSETVLI.asTypeOf(new InstVType), 
     firstVsetInstField.ZIMM_VSETIVLI.asTypeOf(new InstVType))
@@ -74,30 +69,19 @@ class VTypeGen(implicit p: Parameters) extends XSModule{
 
   when(io.commitVType.hasVsetvl) {
     // when vsetvl instruction commit, also update vtypeSpec, because vsetvl flush pipe
-    lastSpecVTypeNext.valid := true.B
-    lastSpecVTypeNext.bits := vtypeSpec
     vtypeSpecNext := io.vsetvlVType
   }.elsewhen(io.walkVType.valid) {
-    lastSpecVTypeNext.valid := false.B
     vtypeSpecNext := io.walkVType.bits
   }.elsewhen(io.redirect && io.commitVType.vtype.valid) {
     // when redirect and commit both coming, we should use commit vtype
-    lastSpecVTypeNext.valid := false.B
     vtypeSpecNext := io.commitVType.vtype.bits
   }.elsewhen(io.redirect && !io.commitVType.vtype.valid) {
-    lastSpecVTypeNext.valid := false.B
     vtypeSpecNext := vtypeArch
   }.elsewhen(inHasVset && io.canUpdateVType) {
-    lastSpecVTypeNext.valid := true.B
-    lastSpecVTypeNext.bits := vtypeSpec
     vtypeSpecNext := vtypeNew
-  }.otherwise {
-    lastSpecVTypeNext.valid := false.B
   }
 
   io.vtype := vtypeSpec
-  io.specVtype := vtypeSpec
-  io.lastSpecVType := lastSpecVType
 
   // just make verilog more readable
   dontTouch(isVsetVec)
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
index fde0f8d2190..349bc76c636 100644
--- a/src/main/scala/xiangshan/backend/rob/Rob.scala
+++ b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -79,10 +79,6 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
         val hasVsetvl = Output(Bool())
       }
     }
-    val fromDecode = new Bundle {
-      val lastSpecVType = Flipped(Valid(new VType))
-      val specVtype = Input(new VType)
-    }
     val readGPAMemAddr = ValidIO(new Bundle {
       val ftqPtr = new FtqPtr()
       val ftqOffset = UInt(log2Up(PredictWidth).W)
@@ -290,8 +286,6 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   io.toDecode.isResumeVType := vtypeBuffer.io.toDecode.isResumeVType
   io.toDecode.commitVType := vtypeBuffer.io.toDecode.commitVType
   io.toDecode.walkVType := vtypeBuffer.io.toDecode.walkVType
-  vtypeBuffer.io.fromDecode.lastSpecVType := io.fromDecode.lastSpecVType
-  vtypeBuffer.io.fromDecode.specVtype := io.fromDecode.specVtype
 
   // When blockBackward instruction leaves Rob (commit or walk), hasBlockBackward should be set to false.B
   // To reduce registers usage, for hasBlockBackward cases, we allow enqueue after ROB is empty.
diff --git a/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala b/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
index f0f6abcfad3..6ad9136a0c7 100644
--- a/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
+++ b/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
@@ -53,11 +53,6 @@ class VTypeBufferIO(size: Int)(implicit p: Parameters) extends XSBundle {
     }
   })
 
-  val fromDecode = new Bundle {
-    val lastSpecVType = Flipped(Valid(new VType))
-    val specVtype = Input(new VType)
-  }
-
   val status = Output(new Bundle {
     val walkEnd = Bool()
   })
@@ -108,15 +103,13 @@ class VTypeBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasCi
   private val walkPtrNext = Wire(new VTypeBufferPtr)
   private val walkPtrVecNext = VecInit((0 until CommitWidth).map(x => walkPtrNext + x.U))
 
-  private val enqVType = WireInit(0.U.asTypeOf(new (VType)))
-  when(io.fromDecode.lastSpecVType.valid) {
-    enqVType := io.fromDecode.lastSpecVType.bits
-  }.otherwise {
-    enqVType := io.fromDecode.specVtype
-  }
+  // get enque vtypes in io.req
+  private val enqVTypes = VecInit(io.req.map(req => req.bits.vpu.vtype))
+  private val enqValids = VecInit(io.req.map(_.valid))
+  private val enqVType = PriorityMux(enqValids.zip(enqVTypes).map { case (valid, vtype) => valid -> vtype })
 
   private val walkPtrSnapshots = SnapshotGenerator(enqPtr, io.snpt.snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec)
-  private val walkVtypeSnapshots = SnapshotGenerator(enqVType, io.snpt.snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec)
+  private val walkVTypeSnapshots = SnapshotGenerator(enqVType, io.snpt.snptEnq, io.snpt.snptDeq, io.redirect.valid, io.snpt.flushVec)
 
   private val robWalkEndReg = RegInit(false.B)
   private val robWalkEnd = io.fromRob.walkEnd || robWalkEndReg
@@ -165,7 +158,11 @@ class VTypeBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasCi
 
   walkPtr := walkPtrNext
 
-  private val useSnapshot = (state === s_idle && stateNext === s_walk) || (state === s_walk && io.snpt.useSnpt && io.redirect.valid)
+  private val useSnapshotNext = WireInit(false.B)
+
+  useSnapshotNext := (state === s_idle && stateNext === s_walk) || (state === s_walk && io.snpt.useSnpt && io.redirect.valid)
+  private val useSnapshot = RegNext(useSnapshotNext)
+  private val snapshotVType = RegEnable(walkVTypeSnapshots(snptSelect), useSnapshotNext)
 
   // update enq ptr
   private val enqPtrNext = Mux(
@@ -280,7 +277,7 @@ class VTypeBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasCi
   }.elsewhen (useSnapshot) {
     // use snapshot vtype
     decodeResumeVType.valid := true.B
-    decodeResumeVType.bits := walkVtypeSnapshots(snptSelect)
+    decodeResumeVType.bits := snapshotVType
   }.elsewhen (state === s_walk && walkCount =/= 0.U) {
     decodeResumeVType.valid := true.B
     decodeResumeVType.bits := newestVType