Skip to content
View eehrich's full-sized avatar

Block or report eehrich

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
4 stars written in Verilog
Clear filter

Verilog Ethernet components for FPGA implementation

Verilog 2,463 731 Updated Feb 27, 2025

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog 672 101 Updated Feb 23, 2025

Simulation only cartridge NeoGeo hardware definition

Verilog 90 12 Updated Aug 13, 2021

Vexriscv on Stratix10 FPGA board using HyperFlex Techniques

Verilog 3 2 Updated Feb 26, 2021