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gfxboard.cpp
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gfxboard.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Cirrus Logic based graphics board emulation
*
* Copyright 2013 Toni Wilen
*
*/
#define VRAMLOG 0
#define MEMLOGR 0
#define MEMLOGW 0
#define MEMLOGINDIRECT 0
#define REGDEBUG 0
#define MEMDEBUG 0
#define MEMDEBUGMASK 0x7fffff
#define MEMDEBUGTEST 0x3fc000
#define MEMDEBUGCLEAR 0
#define PICASSOIV_DEBUG_IO 0
#if MEMLOGR
static bool memlogr = true;
static bool memlogw = true;
#endif
#define BYTESWAP_WORD -1
#define BYTESWAP_LONG 1
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "debug.h"
#include "custom.h"
#include "newcpu.h"
#include "picasso96.h"
#include "statusline.h"
#include "rommgr.h"
#include "zfile.h"
#include "gfxboard.h"
#include "rommgr.h"
#include "xwin.h"
#include "devices.h"
#include "gfxfilter.h"
#include "pcem/device.h"
#include "pcem/vid_s3_virge.h"
#include "pcem/vid_cl5429.h"
#include "pcem/vid_s3.h"
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/vga.h"
#define MONITOR_SWITCH_DELAY 25
#define GFXBOARD_AUTOCONFIG_SIZE 131072
#define BOARD_REGISTERS_SIZE 0x00010000
#define BOARD_MANUFACTURER_PICASSO 2167
#define BOARD_MODEL_MEMORY_PICASSOII 11
#define BOARD_MODEL_REGISTERS_PICASSOII 12
#define BOARD_MODEL_MEMORY_PICASSOIV 24
#define BOARD_MODEL_REGISTERS_PICASSOIV 23
#define PICASSOIV_REG 0x00600000
#define PICASSOIV_IO 0x00200000
#define PICASSOIV_VRAM1 0x01000000
#define PICASSOIV_VRAM2 0x00800000
#define PICASSOIV_ROM_OFFSET 0x0200
#define PICASSOIV_FLASH_OFFSET 0x8000
#define PICASSOIV_FLASH_BANK 0x8000
#define PICASSOIV_MAX_FLASH (GFXBOARD_AUTOCONFIG_SIZE - 32768)
#define PICASSOIV_BANK_UNMAPFLASH 2
#define PICASSOIV_BANK_MAPRAM 4
#define PICASSOIV_BANK_FLASHBANK 128
#define PICASSOIV_INT_VBLANK 128
#define BOARD_MANUFACTURER_PICCOLO 2195
#define BOARD_MODEL_MEMORY_PICCOLO 5
#define BOARD_MODEL_REGISTERS_PICCOLO 6
#define BOARD_MODEL_MEMORY_PICCOLO64 10
#define BOARD_MODEL_REGISTERS_PICCOLO64 11
#define BOARD_MANUFACTURER_SPECTRUM 2193
#define BOARD_MODEL_MEMORY_SPECTRUM 1
#define BOARD_MODEL_REGISTERS_SPECTRUM 2
struct gfxboard
{
int id;
const TCHAR *name;
const TCHAR *manufacturername;
const TCHAR *configname;
int manufacturer;
int model_memory;
int model_registers;
int serial;
int vrammin;
int vrammax;
int banksize;
int chiptype;
int configtype;
int irq;
bool swap;
uae_u32 romtype;
uae_u8 er_type;
struct gfxboard_func *func;
device_t *pcemdev;
};
#define ISP4() (gb->rbc->rtgmem_type == GFXBOARD_ID_PICASSO4_Z2 || gb->rbc->rtgmem_type == GFXBOARD_ID_PICASSO4_Z3)
// Picasso II: 8* 4x256 (1M) or 16* 4x256 (2M)
// Piccolo: 8* 4x256 + 2* 16x256 (2M)
static const struct gfxboard boards[] =
{
{
GFXBOARD_ID_A2410,
_T("A2410"), _T("Commodore"), _T("A2410"),
1030, 0, 0,
0x00000000, 0x00200000, 0x00200000, 0x10000, 0, 0, 2, false,
0, 0xc1, &a2410_func
},
{
GFXBOARD_ID_SPECTRUM_Z2,
_T("Spectrum 28/24 Zorro II"), _T("Great Valley Products"), _T("Spectrum28/24_Z2"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 2, 6, true,
0, 0, NULL, &gd5428_swapped_device
},
{
GFXBOARD_ID_SPECTRUM_Z3,
_T("Spectrum 28/24 Zorro III"), _T("Great Valley Products"), _T("Spectrum28/24_Z3"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 3, 6, true,
0, 0, NULL, &gd5428_swapped_device
},
{
GFXBOARD_ID_PICCOLO_Z2,
_T("Piccolo Zorro II"), _T("Ingenieurbüro Helfrich"), _T("Piccolo_Z2"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 2, 6, true,
0, 0, NULL, &gd5426_swapped_device
},
{
GFXBOARD_ID_PICCOLO_Z3,
_T("Piccolo Zorro III"), _T("Ingenieurbüro Helfrich"), _T("Piccolo_Z3"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 3, 6, true,
0, 0, NULL, &gd5426_swapped_device
},
{
GFXBOARD_ID_SD64_Z2,
_T("Piccolo SD64 Zorro II"), _T("Ingenieurbüro Helfrich"), _T("PiccoloSD64_Z2"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5434, 2, 6, true,
0, 0, NULL, &gd5434_vlb_swapped_device
},
{
GFXBOARD_ID_SD64_Z3,
_T("Piccolo SD64 Zorro III"), _T("Ingenieurbüro Helfrich"), _T("PiccoloSD64_Z3"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5434, 3, 6, true,
0, 0, NULL, &gd5434_vlb_swapped_device
},
{
GFXBOARD_ID_CV64_Z3,
_T("CyberVision 64 Zorro III"), _T("Phase 5"), _T("CV64_Z3"),
8512, 34, 0,
0x00000000, 0x00200000, 0x00400000, 0x20000000, 0, 3, 2, false,
0, 0, NULL, &s3_cybervision_trio64_device
},
{
GFXBOARD_ID_CV643D_Z2,
_T("CyberVision 64/3D Zorro II"), _T("Phase 5"), _T("CV643D_Z2"),
8512, 67, 0,
0x00000000, 0x00400000, 0x00400000, 0x00400000, 0, 2, 2, false,
0, 0, NULL, &s3_virge_375_device
},
{
GFXBOARD_ID_CV643D_Z3,
_T("CyberVision 64/3D Zorro III"), _T("Phase 5"), _T("CV643D_Z3"),
8512, 67, 0,
0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, 3, 2, false,
0, 0, NULL, &s3_virge_375_device
},
{
GFXBOARD_ID_PICASSO2,
_T("Picasso II"), _T("Village Tronic"), _T("PicassoII"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, 2, 0, false,
0, 0, NULL, &gd5426_device
},
{
GFXBOARD_ID_PICASSO2PLUS,
_T("Picasso II+"), _T("Village Tronic"), _T("PicassoII+"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, 2, 2, false,
0, 0, NULL, &gd5428_device
},
{
GFXBOARD_ID_PICASSO4_Z2,
_T("Picasso IV Zorro II"), _T("Village Tronic"), _T("PicassoIV_Z2"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, BOARD_MODEL_REGISTERS_PICASSOIV,
0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, 2, 2, false,
ROMTYPE_PICASSOIV,
0, NULL, &gd5446_device
},
{
GFXBOARD_ID_PICASSO4_Z3,
_T("Picasso IV Zorro III"), _T("Village Tronic"), _T("PicassoIV_Z3"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, 0,
0x00000000, 0x00400000, 0x00400000, 0x02000000, CIRRUS_ID_CLGD5446, 3, 2, false,
ROMTYPE_PICASSOIV,
0, NULL, &gd5446_device
},
{
GFXBOARD_ID_HARLEQUIN,
_T("Harlequin"), _T("ACS"), _T("Harlequin_PAL"),
2118, 100, 0,
0x00000000, 0x00200000, 0x00200000, 0x10000, 0, 0, 2, false,
ROMTYPE_HARLEQUIN, 0xc2, &harlequin_func
},
#if 0
{
_T("Resolver"), _T("DMI"), _T("Resolver"),
2129, 1, 0,
0x00000000, 0x00200000, 0x00200000, 0x10000, 0, 0, 2, false,
0, 0xc1, &a2410_func
},
#endif
{
GFXBOARD_ID_VGA,
_T("x86 bridgeboard VGA"), _T("x86"), _T("VGA"),
0, 0, 0,
0x00000000, 0x00100000, 0x00200000, 0x00000000, CIRRUS_ID_CLGD5426, 0, 0, false,
ROMTYPE_x86_VGA
},
{
NULL
}
};
struct rtggfxboard
{
bool active;
int rtg_index;
int monitor_id;
struct rtgboardconfig *rbc;
TCHAR memorybankname[40];
TCHAR memorybanknamenojit[40];
TCHAR wbsmemorybankname[40];
TCHAR lbsmemorybankname[40];
TCHAR regbankname[40];
int configured_mem, configured_regs;
const struct gfxboard *board;
uae_u8 expamem_lo;
uae_u8 *automemory;
uae_u32 banksize_mask;
uaecptr io_start, io_end;
uaecptr mem_start[2], mem_end[2];
uae_u8 picassoiv_bank, picassoiv_flifi;
uae_u8 p4autoconfig[256];
struct zfile *p4rom;
bool p4z2;
uae_u32 p4_mmiobase;
uae_u32 p4_special_mask;
uae_u32 p4_special_start;
uae_u32 p4_vram_bank[2];
uae_u32 device_data;
CirrusVGAState vga;
uae_u8 *vram, *vramend, *vramrealstart;
int vram_start_offset;
int vrammask;
uae_u32 gfxboardmem_start;
bool monswitch_current, monswitch_new;
bool monswitch_keep_trying;
bool monswitch_reset;
int monswitch_delay;
int fullrefresh;
int resolutionchange;
uae_u8 *gfxboard_surface, *fakesurface_surface;
bool gfxboard_vblank;
int gfxboard_intena;
bool vram_enabled, vram_offset_enabled;
hwaddr vram_offset[2];
uae_u8 cirrus_pci[0x44];
uae_u8 p4i2c;
uae_u8 p4_pci[0x44];
int vga_width, vga_height;
bool vga_refresh_active;
bool vga_changed;
int device_settings;
uae_u32 vgaioregionptr, vgavramregionptr, vgabank0regionptr, vgabank1regionptr;
const MemoryRegionOps *vgaio, *vgaram, *vgalowram, *vgammio;
MemoryRegion vgaioregion, vgavramregion;
DisplaySurface gfxsurface, fakesurface;
addrbank gfxboard_bank_memory;
addrbank gfxboard_bank_memory_nojit;
addrbank gfxboard_bank_wbsmemory;
addrbank gfxboard_bank_lbsmemory;
addrbank gfxboard_bank_nbsmemory;
addrbank gfxboard_bank_registers;
addrbank gfxboard_bank_special;
addrbank gfxboard_bank_vram_pcem;
addrbank gfxboard_bank_vram_normal_pcem;
addrbank gfxboard_bank_vram_wordswap_pcem;
addrbank gfxboard_bank_vram_longswap_pcem;
addrbank gfxboard_bank_vram_cv_1_pcem;
addrbank gfxboard_bank_vram_p4z2_pcem;
addrbank gfxboard_bank_io_pcem;
addrbank gfxboard_bank_io_swap_pcem;
addrbank gfxboard_bank_io_swap2_pcem;
addrbank gfxboard_bank_pci_pcem;
addrbank gfxboard_bank_mmio_pcem;
addrbank gfxboard_bank_mmio_wbs_pcem;
addrbank gfxboard_bank_mmio_lbs_pcem;
addrbank gfxboard_bank_special_pcem;
addrbank *gfxmem_bank;
uae_u8 *vram_back;
struct autoconfig_info *aci;
struct gfxboard_func *func;
device_t *pcemdev;
void *pcemobject, *pcemobject2;
int pcem_mmio_offset;
int pcem_mmio_mask;
bool pcem_pci_configured;
int pcem_data[2];
int pcem_vram_offset;
int pcem_vram_mask;
int pcem_io_mask;
int pcem_vblank;
bool p4_revb;
void *userdata;
};
static struct rtggfxboard rtggfxboards[MAX_RTG_BOARDS];
static struct rtggfxboard *only_gfx_board;
static int rtg_visible[MAX_AMIGADISPLAYS];
static int rtg_initial[MAX_AMIGADISPLAYS];
static int total_active_gfx_boards;
static int vram_ram_a8;
static DisplaySurface fakesurface;
DECLARE_MEMORY_FUNCTIONS(gfxboard);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mem_nojit);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, bsmem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, wbsmem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, lbsmem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, nbsmem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, regs);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboards, regs);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_normal_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_wordswap_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_longswap_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_cv_1_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, vram_p4z2_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, io_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, io_swap_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, io_swap2_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, pci_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mmio_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mmio_wbs_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, mmio_lbs_pcem);
DECLARE_MEMORY_FUNCTIONS_WITH_SUFFIX(gfxboard, special_pcem);
static const addrbank tmpl_gfxboard_bank_memory = {
gfxboard_lget_mem, gfxboard_wget_mem, gfxboard_bget_mem,
gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem,
gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
gfxboard_lget_mem, gfxboard_wget_mem,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL, 0, 0
};
static const addrbank tmpl_gfxboard_bank_memory_nojit = {
gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit, gfxboard_bget_mem_nojit,
gfxboard_lput_mem_nojit, gfxboard_wput_mem_nojit, gfxboard_bput_mem_nojit,
gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
gfxboard_lget_mem_nojit, gfxboard_wget_mem_nojit,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_CACHE_ENABLE_ALL, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_wbsmemory = {
gfxboard_lget_wbsmem, gfxboard_wget_wbsmem, gfxboard_bget_wbsmem,
gfxboard_lput_wbsmem, gfxboard_wput_wbsmem, gfxboard_bput_wbsmem,
gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
gfxboard_lget_wbsmem, gfxboard_wget_wbsmem,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE | ABFLAG_CACHE_ENABLE_ALL, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_lbsmemory = {
gfxboard_lget_lbsmem, gfxboard_wget_lbsmem, gfxboard_bget_lbsmem,
gfxboard_lput_lbsmem, gfxboard_wput_lbsmem, gfxboard_bput_lbsmem,
gfxboard_xlate, gfxboard_check, NULL, NULL, NULL,
gfxboard_lget_lbsmem, gfxboard_wget_lbsmem,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE | ABFLAG_CACHE_ENABLE_ALL, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_nbsmemory = {
gfxboard_lget_nbsmem, gfxboard_wget_nbsmem, gfxboard_bget_bsmem,
gfxboard_lput_nbsmem, gfxboard_wput_nbsmem, gfxboard_bput_bsmem,
gfxboard_xlate, gfxboard_check, NULL, NULL, _T("Picasso IV banked VRAM"),
gfxboard_lget_nbsmem, gfxboard_wget_nbsmem,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE | ABFLAG_CACHE_ENABLE_ALL, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_registers = {
gfxboard_lget_regs, gfxboard_wget_regs, gfxboard_bget_regs,
gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs,
default_xlate, default_check, NULL, NULL, NULL,
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_special = {
gfxboards_lget_regs, gfxboards_wget_regs, gfxboards_bget_regs,
gfxboards_lput_regs, gfxboards_wput_regs, gfxboards_bput_regs,
default_xlate, default_check, NULL, NULL, _T("Picasso IV MISC"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_pcem = {
gfxboard_lget_vram_pcem, gfxboard_wget_vram_pcem, gfxboard_bget_vram_pcem,
gfxboard_lput_vram_pcem, gfxboard_wput_vram_pcem, gfxboard_bput_vram_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_normal_pcem = {
gfxboard_lget_vram_normal_pcem, gfxboard_wget_vram_normal_pcem, gfxboard_bget_vram_normal_pcem,
gfxboard_lput_vram_normal_pcem, gfxboard_wput_vram_normal_pcem, gfxboard_bput_vram_normal_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM (DIRECT)"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_wordswap_pcem = {
gfxboard_lget_vram_wordswap_pcem, gfxboard_wget_vram_wordswap_pcem, gfxboard_bget_vram_wordswap_pcem,
gfxboard_lput_vram_wordswap_pcem, gfxboard_wput_vram_wordswap_pcem, gfxboard_bput_vram_wordswap_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM (WORDSWAP)"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_longswap_pcem = {
gfxboard_lget_vram_longswap_pcem, gfxboard_wget_vram_longswap_pcem, gfxboard_bget_vram_longswap_pcem,
gfxboard_lput_vram_longswap_pcem, gfxboard_wput_vram_longswap_pcem, gfxboard_bput_vram_longswap_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM (LONGSWAP)"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_cv_1_pcem = {
gfxboard_lget_vram_cv_1_pcem, gfxboard_wget_vram_cv_1_pcem, gfxboard_bget_vram_cv_1_pcem,
gfxboard_lput_vram_cv_1_pcem, gfxboard_wput_vram_cv_1_pcem, gfxboard_bput_vram_cv_1_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM (CV64)"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_vram_p4z2_pcem = {
gfxboard_lget_vram_p4z2_pcem, gfxboard_wget_vram_p4z2_pcem, gfxboard_bget_vram_p4z2_pcem,
gfxboard_lput_vram_p4z2_pcem, gfxboard_wput_vram_p4z2_pcem, gfxboard_bput_vram_p4z2_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA VRAM (PIVZ2)"),
dummy_lgeti, dummy_wgeti,
ABFLAG_RAM | ABFLAG_THREADSAFE | ABFLAG_PPCIOSPACE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_io_pcem = {
gfxboard_lget_io_pcem, gfxboard_wget_io_pcem, gfxboard_bget_io_pcem,
gfxboard_lput_io_pcem, gfxboard_wput_io_pcem, gfxboard_bput_io_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA IO SWAP"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_io_swap_pcem = {
gfxboard_lget_io_swap_pcem, gfxboard_wget_io_swap_pcem, gfxboard_bget_io_swap_pcem,
gfxboard_lput_io_swap_pcem, gfxboard_wput_io_swap_pcem, gfxboard_bput_io_swap_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA IO SWAP"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_io_swap2_pcem = {
gfxboard_lget_io_swap2_pcem, gfxboard_wget_io_swap2_pcem, gfxboard_bget_io_swap2_pcem,
gfxboard_lput_io_swap2_pcem, gfxboard_wput_io_swap2_pcem, gfxboard_bput_io_swap2_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA IO SWAP2"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_pci_pcem = {
gfxboard_lget_pci_pcem, gfxboard_wget_pci_pcem, gfxboard_bget_pci_pcem,
gfxboard_lput_pci_pcem, gfxboard_wput_pci_pcem, gfxboard_bput_pci_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA PCI"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_mmio_pcem = {
gfxboard_lget_mmio_pcem, gfxboard_wget_mmio_pcem, gfxboard_bget_mmio_pcem,
gfxboard_lput_mmio_pcem, gfxboard_wput_mmio_pcem, gfxboard_bput_mmio_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA MMIO"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_mmio_wbs_pcem = {
gfxboard_lget_mmio_wbs_pcem, gfxboard_wget_mmio_wbs_pcem, gfxboard_bget_mmio_wbs_pcem,
gfxboard_lput_mmio_wbs_pcem, gfxboard_wput_mmio_wbs_pcem, gfxboard_bput_mmio_wbs_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA MMIO WORDSWAP"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_mmio_lbs_pcem = {
gfxboard_lget_mmio_lbs_pcem, gfxboard_wget_mmio_lbs_pcem, gfxboard_bget_mmio_lbs_pcem,
gfxboard_lput_mmio_lbs_pcem, gfxboard_wput_mmio_lbs_pcem, gfxboard_bput_mmio_lbs_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA MMIO WORDSWAP"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static const addrbank tmpl_gfxboard_bank_special_pcem = {
gfxboard_lget_special_pcem, gfxboard_wget_special_pcem, gfxboard_bget_special_pcem,
gfxboard_lput_special_pcem, gfxboard_wput_special_pcem, gfxboard_bput_special_pcem,
default_xlate, default_check, NULL, NULL, _T("PCem SVGA SPC"),
dummy_lgeti, dummy_wgeti,
ABFLAG_IO | ABFLAG_SAFE, S_READ, S_WRITE
};
static void ew(struct rtggfxboard *gb, int addr, uae_u32 value)
{
addr &= 0xffff;
if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
gb->automemory[addr] = (value & 0xf0);
gb->automemory[addr + 2] = (value & 0x0f) << 4;
} else {
gb->automemory[addr] = ~(value & 0xf0);
gb->automemory[addr + 2] = ~((value & 0x0f) << 4);
}
}
int gfxboard_get_devnum(struct uae_prefs *p, int index)
{
int devnum = 0;
uae_u32 romtype = gfxboard_get_romtype(&p->rtgboards[index]);
if (!romtype)
return devnum;
for (int i = 0; i < index; i++) {
if (gfxboard_get_romtype(&p->rtgboards[i]) == romtype)
devnum++;
}
return devnum;
}
void gfxboard_get_a8_vram(int index)
{
addrbank *ab = gfxmem_banks[index];
if (vram_ram_a8 > 0) {
addrbank *prev = gfxmem_banks[vram_ram_a8 - 1];
ab->baseaddr = prev->baseaddr;
} else {
mapped_malloc(ab);
vram_ram_a8 = index + 1;
}
}
void gfxboard_free_vram(int index)
{
addrbank *ab = gfxmem_banks[index];
if (vram_ram_a8 - 1 == index || vram_ram_a8 == 0) {
mapped_free(ab);
}
if (vram_ram_a8 - 1 == index)
vram_ram_a8 = 0;
}
extern uae_u8 *getpcembuffer32(int, int, int);
// PCEM
void video_blit_memtoscreen(int x, int y, int y1, int y2, int w, int h)
{
for (int i = 0; i < MAX_RTG_BOARDS; i++) {
struct rtggfxboard *gb = &rtggfxboards[i];
if (gb->pcemdev && gb->pcemobject) {
if (rtg_visible[gb->monitor_id] >= 0 && gb->monswitch_delay == 0 && gb->monswitch_current == gb->monswitch_new) {
if (gb->gfxboard_surface == NULL) {
gb->gfxboard_surface = gfx_lock_picasso(gb->monitor_id, false, false);
}
if (gb->gfxboard_surface) {
struct picasso_vidbuf_description *vidinfo = &picasso_vidinfo[gb->monitor_id];
for (int yy = y1; yy < y2 && yy < vidinfo->height; yy++) {
uae_u8 *d = gb->gfxboard_surface + yy * vidinfo->rowbytes;
uae_u8 *s = getpcembuffer32(x, y, yy);
int ww = w > vidinfo->width ? vidinfo->width : w;
memcpy(d, s, ww * vidinfo->pixbytes);
}
}
}
}
}
}
static int gfxboard_pcem_poll(struct rtggfxboard *gb)
{
extern int svga_poll(void *p);
return svga_poll(gb->pcemobject2);
}
static void gfxboard_hsync_handler(void)
{
for (int i = 0; i < MAX_RTG_BOARDS; i++) {
struct rtggfxboard *gb = &rtggfxboards[i];
if (!gb->active)
continue;
if (gb->func && gb->userdata) {
gb->func->hsync(gb->userdata);
}
if (gb->pcemdev && gb->pcemobject && !gb->pcem_vblank) {
extern int svga_get_vtotal(void);
static int pollcnt;
int pollsize = svga_get_vtotal() * 256 / 300;
if (pollsize < 256)
pollsize = 256;
pollcnt += pollsize;
while (pollcnt >= 256) {
if (gfxboard_pcem_poll(gb)) {
gb->pcem_vblank = 1;
pollcnt &= 0xff;
break;
}
pollcnt -= 256;
}
}
}
}
static void init_board (struct rtggfxboard *gb)
{
struct rtgboardconfig *rbc = gb->rbc;
int vramsize = gb->board->vrammax;
int chiptype = gb->board->chiptype;
if (gb->board->romtype == ROMTYPE_x86_VGA) {
struct romconfig *rc = get_device_romconfig(&currprefs, gb->board->romtype, 0);
chiptype = CIRRUS_ID_CLGD5426;
if (rc && rc->device_settings == 1) {
chiptype = CIRRUS_ID_CLGD5429;
}
}
gb->active = true;
gb->vga_width = 0;
gb->vga_height = 0;
mapped_free(gb->gfxmem_bank);
gb->vram_start_offset = 0;
if (ISP4() && !gb->p4z2) { // JIT direct compatibility hack
gb->vram_start_offset = 0x01000000;
}
vramsize += gb->vram_start_offset;
xfree (gb->fakesurface_surface);
gb->fakesurface_surface = xmalloc (uae_u8, 4 * 10000);
gb->vram_offset[0] = gb->vram_offset[1] = 0;
gb->vram_enabled = true;
gb->vram_offset_enabled = false;
gb->gfxmem_bank->reserved_size = vramsize;
gb->gfxmem_bank->start = gb->gfxboardmem_start;
if (gb->board->manufacturer) {
gb->gfxmem_bank->label = _T("*");
mapped_malloc(gb->gfxmem_bank);
} else {
gb->gfxmem_bank->label = _T("*");
gb->vram_back = xmalloc(uae_u8, vramsize);
if (&get_mem_bank(0x800000) == &dummy_bank)
gb->gfxmem_bank->start = 0x800000;
else
gb->gfxmem_bank->start = 0xa00000;
gfxboard_get_a8_vram(gb->rbc->rtg_index);
}
gb->vrammask = vramsize - 1;
gb->vram = gb->gfxmem_bank->baseaddr;
gb->vramend = gb->gfxmem_bank->baseaddr + vramsize;
gb->vramrealstart = gb->vram;
gb->vram += gb->vram_start_offset;
gb->vramend += gb->vram_start_offset;
//gb->gfxmem_bank->baseaddr = gb->vram;
// restore original value because this is checked against
// configured size in expansion.cpp
gb->gfxmem_bank->allocated_size = rbc->rtgmem_size;
gb->gfxmem_bank->reserved_size = rbc->rtgmem_size;
gb->vga.vga.vram_size_mb = rbc->rtgmem_size >> 20;
gb->vgaioregion.opaque = &gb->vgaioregionptr;
gb->vgaioregion.data = gb;
gb->vgavramregion.opaque = &gb->vgavramregionptr;
gb->vgavramregion.data = gb;
gb->vga.vga.vram.opaque = &gb->vgavramregionptr;
gb->vga.vga.vram.data = gb;
gb->vga.cirrus_vga_io.data = gb;
gb->vga.low_mem_container.data = gb;
gb->vga.low_mem.data = gb;
gb->vga.cirrus_bank[0].data = gb;
gb->vga.cirrus_bank[1].data = gb;
gb->vga.cirrus_linear_io.data = gb;
gb->vga.cirrus_linear_bitblt_io.data = gb;
gb->vga.cirrus_mmio_io.data = gb;
gb->gfxsurface.data = gb;
gb->fakesurface.data = gb;
vga_common_init(&gb->vga.vga);
gb->vga.vga.con = (void*)gb;
cirrus_init_common(&gb->vga, chiptype, 0, NULL, NULL, gb->board->manufacturer == 0, gb->board->romtype == ROMTYPE_x86_VGA);
gb->pcemdev = gb->board->pcemdev;
gb->pcem_pci_configured = false;
if (gb->pcemdev) {
extern void initpcemvideo(void*, bool);
extern void *svga_get_object(void);
initpcemvideo(gb, gb->board->swap);
gb->pcemobject = gb->pcemdev->init();
gb->pcemobject2 = svga_get_object();
}
picasso_allocatewritewatch(gb->rbc->rtg_index, gb->rbc->rtgmem_size);
device_add_hsync(gfxboard_hsync_handler);
}
static int GetBytesPerPixel(RGBFTYPE RGBfmt)
{
switch (RGBfmt)
{
case RGBFB_CLUT:
return 1;
case RGBFB_A8R8G8B8:
case RGBFB_A8B8G8R8:
case RGBFB_R8G8B8A8:
case RGBFB_B8G8R8A8:
return 4;
case RGBFB_B8G8R8:
case RGBFB_R8G8B8:
return 3;
case RGBFB_R5G5B5:
case RGBFB_R5G6B5:
case RGBFB_R5G6B5PC:
case RGBFB_R5G5B5PC:
case RGBFB_B5G6R5PC:
case RGBFB_B5G5R5PC:
return 2;
}
return 0;
}
static void gfxboard_unlock(struct rtggfxboard *gb)
{
if (gb->gfxboard_surface) {
gfx_unlock_picasso(gb->monitor_id, true);
gb->gfxboard_surface = NULL;
}
}
static bool gfxboard_setmode(struct rtggfxboard *gb, struct gfxboard_mode *mode)
{
struct amigadisplay *ad = &adisplays[gb->monitor_id];
struct picasso96_state_struct *state = &picasso96_state[gb->monitor_id];
state->Width = mode->width;
state->Height = mode->height;
state->VirtualWidth = state->Width;
state->VirtualHeight = state->Height;
int bpp = GetBytesPerPixel(mode->mode);
state->BytesPerPixel = bpp;
state->BytesPerRow = mode->width * bpp;
state->RGBFormat = mode->mode;
write_log(_T("GFXBOARD %dx%dx%d\n"), mode->width, mode->height, bpp);
if (!ad->picasso_requested_on && !ad->picasso_on) {
ad->picasso_requested_on = true;
set_config_changed();
}
gfxboard_unlock(gb);
return true;
}
static void gfxboard_free_slot2(struct rtggfxboard *gb)
{
struct amigadisplay *ad = &adisplays[gb->monitor_id];
gb->active = false;
if (rtg_visible[gb->monitor_id] == gb->rtg_index) {
rtg_visible[gb->monitor_id] = -1;
ad->picasso_requested_on = false;
set_config_changed();
}
if (gb->pcemdev) {
if (gb->pcemobject) {
gb->pcemdev->close(gb->pcemobject);
gb->pcemobject = NULL;
}
}
gb->userdata = NULL;
gb->func = NULL;
xfree(gb->automemory);
gb->automemory = NULL;
}
static const struct gfxboard *find_board(int id)
{
for (int i = 0; boards[i].id; i++) {
if (id == boards[i].id)
return &boards[i];
}
return NULL;
}
bool gfxboard_allocate_slot(int board, int idx)
{
struct rtggfxboard *gb = &rtggfxboards[idx];
const struct gfxboard *gfxb = find_board(board);
if (!gfxb)
return false;
gb->active = true;
gb->rtg_index = idx;
gb->board = gfxb;
return true;
}
void gfxboard_free_slot(int idx)
{
struct rtggfxboard *gb = &rtggfxboards[idx];
gfxboard_free_slot2(gb);
}
static int gfx_temp_bank_idx;
static uae_u32 REGPARAM2 gtb_wget(uaecptr addr)
{
struct rtggfxboard *gb = &rtggfxboards[gfx_temp_bank_idx];
addr &= gb->banksize_mask;
return 0;
}
static uae_u32 REGPARAM2 gtb_bget(uaecptr addr)
{
struct rtggfxboard *gb = &rtggfxboards[gfx_temp_bank_idx];
addr &= gb->banksize_mask;
if (addr < GFXBOARD_AUTOCONFIG_SIZE)
return gb->automemory[addr];
return 0xff;
}
static void REGPARAM2 gtb_bput(uaecptr addr, uae_u32 b)
{
struct rtggfxboard *gb = &rtggfxboards[gfx_temp_bank_idx];
b &= 0xff;
addr &= gb->banksize_mask;
if (addr == 0x48) {
gfx_temp_bank_idx++;
map_banks_z2(gb->gfxmem_bank, expamem_board_pointer >> 16, expamem_board_size >> 16);
gb->func->configured(gb->userdata, expamem_board_pointer);
expamem_next(gb->gfxmem_bank, NULL);
return;
}
if (addr == 0x4c) {
expamem_shutup(gb->gfxmem_bank);
return;
}
}
static void REGPARAM2 gtb_wput(uaecptr addr, uae_u32 b)
{
struct rtggfxboard *gb = &rtggfxboards[gfx_temp_bank_idx];
b &= 0xffff;
addr &= gb->banksize_mask;
if (addr == 0x44) {
gfx_temp_bank_idx++;
map_banks_z3(gb->gfxmem_bank, expamem_board_pointer >> 16, expamem_board_size >> 16);
gb->func->configured(gb->userdata, expamem_board_pointer);
expamem_next(gb->gfxmem_bank, NULL);
return;
}
}
static addrbank gfx_temp_bank =
{
gtb_wget, gtb_wget, gtb_bget,
gtb_wput, gtb_wput, gtb_bput,
default_xlate, default_check, NULL, NULL, _T("GFXBOARD_AUTOCONFIG"),
gtb_wget, gtb_wget,
ABFLAG_IO, S_READ, S_WRITE
};
bool gfxboard_init_board(struct autoconfig_info *aci)
{
const struct gfxboard *gfxb = find_board(aci->prefs->rtgboards[aci->devnum].rtgmem_type);
if (!gfxb)
return false;
struct rtggfxboard *gb = &rtggfxboards[aci->devnum];
gb->func = gfxb->func;
gb->pcemdev = gfxb->pcemdev;
gb->monitor_id = aci->prefs->rtgboards[aci->devnum].monitor_id;
memset(aci->autoconfig_bytes, 0xff, sizeof aci->autoconfig_bytes);
if (!gb->automemory)
gb->automemory = xmalloc(uae_u8, GFXBOARD_AUTOCONFIG_SIZE);
memset(gb->automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
ew(gb, 0x00, gfxb->er_type);
ew(gb, 0x04, gfxb->model_memory);
ew(gb, 0x10, (gfxb->manufacturer >> 8) & 0xff);
ew(gb, 0x14, (gfxb->manufacturer >> 0) & 0xff);
ew(gb, 0x18, (gfxb->serial >> 24) & 0xff);
ew(gb, 0x1c, (gfxb->serial >> 16) & 0xff);
ew(gb, 0x20, (gfxb->serial >> 8) & 0xff);
ew(gb, 0x24, (gfxb->serial >> 0) & 0xff);
memcpy(aci->autoconfig_raw, gb->automemory, sizeof aci->autoconfig_raw);
if (!gb->func->init(aci))
return false;
for(int i = 0; i < sizeof aci->autoconfig_bytes; i++) {
if (aci->autoconfig_bytes[i] != 0xff)
ew(gb, i * 4, aci->autoconfig_bytes[i]);
}
memcpy(aci->autoconfig_raw, gb->automemory, sizeof aci->autoconfig_raw);
if (!aci->doinit)
return true;
gb->banksize_mask = gfxb->banksize - 1;
gb->userdata = aci->userdata;
gb->active = true;
gb->rtg_index = aci->devnum;
gb->board = gfxb;
gfx_temp_bank_idx = aci->devnum;
gb->gfxmem_bank = aci->addrbank;
aci->addrbank = &gfx_temp_bank;
return true;
}
static void vga_update_size_ext(struct rtggfxboard *gb)
{
if (!gb->pcemdev) {
// this forces qemu_console_resize() call
gb->vga.vga.graphic_mode = -1;
gb->vga.vga.monid = gb->monitor_id;
gb->vga.vga.hw_ops->gfx_update(&gb->vga);
}
}
static void gfxboard_set_fullrefresh(struct rtggfxboard *gb, int cnt)
{
gb->fullrefresh = cnt;
if (gb->pcemdev && gb->pcemobject) {
gb->pcemdev->force_redraw(gb->pcemobject);
}
}
static bool gfxboard_setmode_ext(struct rtggfxboard *gb)
{
int bpp;
if (gb->pcemdev) {
bpp = 32;
} else {
bpp = gb->vga.vga.get_bpp(&gb->vga.vga);
if (bpp == 0)
bpp = 8;
vga_update_size_ext(gb);
}
if (gb->vga_width <= 16 || gb->vga_height <= 16)
return false;
struct gfxboard_mode mode;
mode.width = gb->vga_width;
mode.height = gb->vga_height;
mode.mode = RGBFB_NONE;
for (int i = 0; i < RGBFB_MaxFormats; i++) {
RGBFTYPE t = (RGBFTYPE)i;
if (GetBytesPerPixel(t) == bpp / 8) {
mode.mode = t;
break;
}
}
gfxboard_setmode(gb, &mode);
gfx_set_picasso_modeinfo(gb->monitor_id, mode.mode);
gfxboard_set_fullrefresh(gb, 2);